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preliminary technical data a four-channel, 80 msps wcdma receive signal processor (rsp) preliminary technical data a d 6635 features four 80 msps wide band inputs (14 linear bit plus 3 rssi) processes 4 wcdma c h annel s (um t s or cdma2000 1x) or 8 gsm/edge, is136 channels eight i nde pendent di gital rec e ivers in a single package fo ur 16-bi t par a llel ou tp ut p o rts an d f our 8- b i t li nk ports fo ur program mable di gital a g c lo ops wit h 96db ran g e digital re-sa m plin g f o r no n-i n teger deci mati on rates program mable decimati ng fir filters fo ur inter pola t i ng hal f ba nd fi lters program mable atte nua tor co n t rol f o r cli p pre venti on a nd external gai n ra ngi ng via level indica tor flexible control for m u lti - carri er and phase d array 3.3 volt i/o, 2.5 volt cm os cor e user confi gura b le buil t in sel f test (bist) ca pabili ty jtag boundar y scan applications multi - carrier, multi - mode di gital receivers gsm, is136, edge, phs, is95, umts, cdma20 00 micro and pico cell systems, s o ftware ra dios wireless local loop smart ante nna systems in buil ding wir e less telephony re - ra m c oef . filte r nc o i n p u t m a t r i x nc o nc o nc o ra m c oef . filte r ra m c oef . filte r ra m c oef . filte r ch a in terp o l atin g h a l f band fi l t er , i n t e r l eavi n g & a g c ch b in terp o l atin g h a l f ban d f i l t e r , i n t e r l eavi n g & a g c re - s a m p l e r ci c 5 rcic 2 re - s a m p l e r cic5 rcic 2 re - s a m p l e r cic5 rcic 2 re - s a m p l e r cic5 rcic 2 ch a & b o u tp ut m u x ci r c ui t r y c h a nnel 1 c h a nnel 2 c h a nnel 3 c h a nnel 4 po r t b 8- b i t d s p li nk or 16 -b it p a r a llel ou tput con t r o l r c f o u tpu t s c h a . 1, 2, 3 , 4 po r t a 8- b i t d s p li nk or 16 -b it p a r a lle l ou tput con t r o l r c f o u tp uts c h a. 1 , 2, 3, 4 . . . . . to a & b ou t p ut s to a & b o u t pu t po r t s to a & b o u t pu t po r t s to a & b o u t pu t po r t s . . re - ra m c oef . fi l t er nc o e x t e r nal s y nc . c i r c ui t built in self t e s t cir c u i try i n p u t m a t r i x nc o nc o nc o ra m c oef . fi l t er ra m c oef . fi l t er ra m c oef . fi l t er mi cr opor t jt a g rs p cl k ch c in terp o l atin g h a l f band fi l t er , i n te r l ea v i ng & a g c h a l f ban d f i l t e r , i n t e r l eavi n g & a g c cl k re - s a m p l e r ci c 5 rcic 2 re - s a m p l e r ci c 5 rcic 2 re - s a m p l e r ci c 5 rcic 2 re - s a m p l e r ci c 5 rcic 2 c ha c & d o u tp ut m u x ci r c ui t r y c han nel 5 c han nel 6 c han nel 7 c han nel 8 po r t d 8- b i t d s p li nk or 16 -b it p a r a llel ou tput con t r o l r c f o u tpu t s c h a. 5 , 6,7 , 8 po r t c 8- b i t d s p li nk or 16 -b it p a r a llel ou tput con t r o l r c f o u tp uts c ha. 5 , 6,7 , 8 . . . . . to c & d o u t pu t po r t s to c & d o u t pu t po r t s to c & d o u t pu t po r t s to c & d o u t pu t po r t s . . sy nca sy ncc sy ncb sy ncd ch d in terp o l atin g lic - b ex pc [2: 0 ] ien c lic - a inc [ 1 3 :0 ] ind [ 1 3 :0 ] ex pd [2: 0 ] ien d lid - a lid - b inb [ 1 3 :0 ] ex pb [2:0 ] lib - b ien b lib - a ina [ 1 3 :0 ] ex pa [2: 0 ] ien a lia - a lia - b rev. prb 7/25/2002 info rmation furni s h ed by analog dev i ces i s believ ed to be accura te and reliable. how e v e r, no re spon sibili ty is assumed by analo g dev i ces for its use, nor for any infr ingement s o f paten ts or other righ ts of third par ties that m a y result from it s use. n o lice n se i s g r anted by implica t io n or oth e rw ise under any pa tent or patent righ ts o f an alog dev i ces. one technol og y wa y , p. o. box 910 6, nor w ood, m a 0 2062-9106 , u . s. a . tel: 781/329 -4700 www .ana log.com fax: 781/326-87 03 ? a n alog dev i ces, inc., 20 02
preliminary technical data AD6635 product descrip t ion the AD6635 is a m u lti- m ode eight c h a n nel digital receive si gnal pr ocess o r (r sp ) ca pa b l e of p r oce ssi n g up t o f o u r wcdm a c h annels. each cha nnel c o nsists of four cascade d signal-proces sing elem ents: a fre que ncy tra n slator, t w o cic d ecim a t i n g filters, and a programmab l e co efficien t- d ecim a t i n g filter. each inp u t p o rt h a s inpu t lev e l thresho l d detection circuitry and an agc controller for accomm odating large dynam i c ra nges or situations where g a in ran g i n g co nv erters are used . qu ad 16 -b it p a rallel out put p o rt s ac com odat e hi gh dat a rat e w b c d m a ap p lication s . on-ch i p i n terpo l a tin g h a lf b a n d filters can also b e u s ed to fu rt h e r in crease the ou tpu t rate. in add itio n, each paral l e l o u t p ut po rt has a di gi t a l agc f o r o u t put dat a scal i ng. li nk po rt out put s a r e p r o v i d e d t o e n abl e gl ue -l ess interfaces to analog devices ? tigersharc tm dsp c o re. th e ad663 5 is p a rt of an alog dev i ces? softcell? mu lti- carrier tran sceiv e r ch i p set d e sig n e d for co m p atib ility with anal og de vi ce s fam i ly of hi g h sam p l e rat e i f sam p l i ng a d c s (a d66 4 0 / ad 664 4 12 & 14 b it) . th e sof t cell? receiver c o m p rises a di gital re cei ver ca pa ble of di gitizing a n entire s p ectrum of carriers a n d di g itally sel ectin g the carri er o f in terest for t u n i n g and ch ann e l selectio n. th is architecture eliminates redunda nt ra di os i n w i rel e ss base st at i on a ppl i cat i ons . high d y n a m i c rang e d ecim a t i o n filters o f fer a wid e rang e of decim a tion rat e s. t h e r a m-base d arc h itecture allows eas y recon f i g uration for m u lti- m o d e ap p lication s . th e d ecim a t i n g filters rem o ve un wan t ed sign als an d no ise fro m th e ch annel o f in terest. wh en t h e ch ann e l of i n terest o ccup i es less ban d wid t h th an th e inp u t sign al, th is rej ection of o u t - of -ba n d noi se i s cal l e d ?pr o cessi ng ga i n ?. b y usi n g large decim a tion fact ors , this ?proces sing gain? can im prove th e snr o f t h e adc b y 30 db o r m o re. in ad d ition , t h e p r og ramm ab le ram co effici en t filter allows an ti-aliasing , match e d filteri n g , an d static eq u a lization functio n s t o b e co m b in ed i n a sin g l e, co st -effectiv e filter. half b a nd in terpo l atin g fi lters at th e ou tp u t are u s ed in wcdm a ap p lication s to in crease t h e outp u t rate fro m 2 x to 4x o f th e ch ip rate. th e ad66 35 is equip p e d with four ind e p e nd en t au to m a tic g a in con t ro l (agc ) lo op s fo r d i rect in terface to a rake recei ve r. th e ad663 5 is co m p atib le with stand a rd adc co nv erters su ch as t h e a d 6 64x , ad 943x , ad 922 x, and th e ad9 24x fam i lies o f d a ta con v e rters. th e ad663 5 is also co m p atib le wi t h t h e a d 6 6 0 0 di versi t y a d c p r ovi di n g a cost a n d si ze redu ction p a th . 2 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 conte n t s featu r es ............................................................... 1 applic ations ......................................................... 1 product description ................................... 2 architecture .................................................. 5 recomme nded ope r ating conditions ........................................................ 7 gene ral timing charact e ristics 1, 2 ........................................ 8 absolut e maximum ratings 1 ................. 10 pin configuration ...................................... 11 ball configuration .................................. 12 pin functions ................................................. 13 timing diagrams .......................................... 15 input data ports ......................................... 22 input data f o rm at ..................................... 22 input tim i ng ............................................. 22 input enable control ................................. 22 gain switching .......................................... 23 input data s caling ..................................... 24 scaling with fixed-point adcs ................. 24 scaling with floating-point or gain- ranging adcs ........................................... 24 numerically controlled oscillator ...................................................... 25 frequency t r anslation ............................... 25 nco frequency hold-off register .......... 25 phase offset .............................................. 25 nco control register ............................... 25 by-pass ...................................................... 26 phase dither .............................................. 26 am plitude dither ...................................... 26 clear phase accum u lator on hop ............ 26 input enable control ................................. 26 mo d e 00 : blan k on i e n low 26 m ode 0 1 : c l o c k on ie n hi g h 26 m ode 1 0 : c l o c k on ie n tran sitio n to h i g h 2 6 m ode 1 1 : c l o c k on ie n tran sitio n to low 2 6 wb input select ........................................ 27 sync select ................................................ 27 2 nd order rcic filter .................................... 27 rcic2 rejection ........................................ 28 exam ple ca lculations ............................... 28 decim a tion and interpolation registers .................................................... 28 rcic2 scale ............................................... 28 5 th order cic filter ...................................... 29 cic5 rejection .......................................... 29 ram coefficient filter ............................. 30 rcf deci mation register ......................... 30 rcf deci mation phase ............................. 30 rcf filter length ..................................... 30 rcf output scale factor and control register ........................................ 31 interpol a ting half band filters ............................................................... 32 autom atic gain control ........................ 32 the agc loop .......................................... 33 desired signal level mode ....................... 33 desired clipping level mode ................... 35 synchronization ......................................... 35 user configur abl e built in self test (bist) ............................................... 36 ram bist ................................................ 36 channel bist ...................................... 36 chip synchronization ............................... 36 start ........................................................... 37 start w ith no sync ................................... 37 start w ith soft sync .................................. 37 start w ith pin sync ................................... 37 hop ............................................................ 38 set freq no hop ........................................ 38 hop w ith soft sync .................................. 38 hop w ith pin sync .................................... 38 parallel output ports ............................ 38 channel m o de ............................................ 39 agc mode ................................................. 40 master/slave pclk modes ....................... 40 parallel port pin functionality .................. 41 link port .......................................................... 41 link port data form at ............................... 41 link port tim i ng ....................................... 42 tigersharc configuration ..................... 42 AD6635 channe l memory m a p ................ 43 0x00-0x7f: coefficient mem o ry(cmem) ...................................... 43 0x80: channel sleep register .................. 43 0x81: soft_sync register ...................... 43 0x82: pin_sync register ....................... 43 0x83: start hold-off counter .................. 43 0x84: nco frequency hold-off counter ...................................................... 44 0x85: nco frequency register 0 ............ 44 0x86: nco frequency register 1 ............ 44 rev. pr b. 7 / 25/2002 3
preliminary technical data AD6635 0x87: nco phase offse t register ........... 44 0x88: nco control register .................... 44 0x90: rcic2 decim a tion ? 1 (m rcic2 -1) .................................................. 45 0x91: rcic2 interpolation ? 1 (l rcic2 -1) .................................................... 45 0x92: rcic2 scale .................................... 46 0x93: .......................................................... 46 0x94: cic5 decim a tion ? 1 (m cic5 -1) ................................................... 46 0x95: cic5 scale ..................................... 46 0x96: .......................................................... 46 0xa0: rcf decim a tion ? 1 (m rcf - 1) ............................................................... 46 0xa1: rcf decim a tion phase (p rcf ) ......................................................... 46 0xa2: rcf num b er of taps m i nus one (n rcf -1) .............................................. 46 0xa3: rcf coefficient offset (co rcf ) ..................................................... 46 0xa4: rcf control register .................... 46 0xa5: bist register f o r i ........................ 47 0xa6: bist register f o r q ...................... 47 0xa7: bist control register .................. 47 0xa8: ram bist control register ..................................................... 47 0xa9: output control r e gister ................ 47 mem o ry map for input port control registers ................................................................ 48 input port c ontrol registers ..................... 48 0x00 lower threshold a: .......................... 48 0x01 upper threshold a: ........................... 48 0x02 dwell tim e a: ................................... 48 0x03 gain range a control register: .................................................... 48 0x04 lower threshold b: ........................... 49 0x05 upper threshold b: ........................... 49 0x06 dwell tim e b: ................................... 49 0x07 gain range b control register: .................................................... 49 mem o ry map for output port control registers ................................................................ 50 0x08 port a control register .................... 51 0x09 port b control register .................... 52 0x0a agc a control register ................. 52 0x0b agc a hold off counter ................ 52 0x0c agc a desired level ....................... 52 0x0d agc a signal gain ......................... 52 0x0e agc a loop gain ........................... 52 0x0f agc a pole location ...................... 52 0x10 agc a average sa m p les ................ 53 0x11 agc a update decim a tion ............. 53 0x12 agc b control register .................. 53 0x13 agc b hold off counter ................. 53 0x14 agc b desired level ........................ 53 0x15 agc b signal gain .......................... 53 0x16 agc b loop gain ............................ 53 0x17 agc b pole location ...................... 54 0x18 agc b average sam p les ................. 54 0x19 agc b update decim a tion .............. 54 0x1a parallel port control a .................... 54 0x1b link port control a ......................... 54 0x1c parallel port control b .................... 54 0x1d link port control b ......................... 55 0x1e port clock control ........................... 55 microport control .................................... 55 external memory map .............................. 55 access control register(acr) ................. 56 external memory map .............................. 56 microport instructions ............................... 56 channel address register (car) ............. 57 soft_sync control register ................. 57 pin_sync control register .................... 57 sleep con t rol register ............................ 57 data address registers ............................. 58 w r ite sequencing ...................................... 58 read sequencing ....................................... 58 read/w rite chaining ................................. 58 inte l non-m u ltip lexed mode (inm) ........................................................ 58 motorola non-multiplexed mode (mnm) ...................................................... 58 serial port control .................................. 58 serial port t i m i ng specifications ............. 59 sdi0, sdi4 ................................................ 59 sclk0, sclk4 ........................................ 59 jtag boundary scan .................................. 59 internal w r ite access ............................. 60 w r ite pseudocode ...................................... 60 internal read access ............................... 61 read pseudocode ....................................... 61 4 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 rev. pr b. 7 / 25/2002 5 architecture each channel of the AD6635 has four signal processing stages: a frequency translator, second order re-sampling cascaded integrator comb fir filter (rcic2), a fifth order cascaded integrator comb fir filter (cic5) and a ram coefficient fir filter (rcf). multiple modes are supported for clocking data into and out of the chip and provide flexibility for interfacing to a wide variety of digitizers. programming and control is accomplished via serial and / or microprocessor interfaces. frequency translation is accomplished with a 32-bit complex numerically controlled oscill ator (nco). real data entering this stage is sepa rated into in-phase (i) and quadrature (q) components. this stage translates the input signal from a digital intermediate frequency (if) to digital baseband. phase and amplitude dither may be enabled on- chip to improve spurious performance of the nco. a phase-offset word is availa ble to create a known phase relationship between multiple AD6635s or between channels. following frequency translation is a fixed coefficient, high speed, second order, re-sampling cascade integrator comb (rcic2) filter that reduces the sample rate based on the ratio between the decimation and interpolation registers. the next stage is a fifth orde r cascaded integrator comb (cic5) filter whose response is defined by the decimation rate. the purpose of these filters is to reduce the data rate to the final filter stage so that it can calculate more taps per output. the final stage is a sum-of-products fir filter with programmable 20-bit coeffici ents, and decimation rates programmable from 1 to 256 (1-32 in practice). the ram coefficient fir filter (rcf in figure 1) can handle a maximum of 160 taps. the next stage is a fixed coefficient halfband interpolation filter where data from different channels is clubbed together and interpolated by a factor of 2. next an agc section with a gain range of 96.3db is available. this agc section is completely programmable in terms of its response. four each of halfband filters and agc?s are present in the AD6635 as shown in the figure 1. these halfband filters and agc sections can be bypassed or the agc section can be used to provide constant gain. the overall filter response for the AD6635 is the composite of all decimating and interpola ting stages. each successive filter stage is capable of narr ower transition bandwidths but requires a greater number of clk cycles to calculate the output. more decimation in the first filter stage will minimize overall power consumption. data from the chip is interfaced to the dsp via either a high-speed parallel port or a tigersharc compatible link port. each channel has separate parallel and link ports. figure 2a illustrates the basic function of the AD6635: to select and filter a single channel from a wide input spectrum. the frequency translator ?tunes? the desired carrier to baseband. figure 2b shows the combined filter response of the rcic2, cic5, and rcf.
preliminary technical data AD6635 6 rev. pr b. 7 / 25/2002 dc fs / 1 6 fs / 8 3f s / 1 6 fs / 4 5f s / 1 6 3f s / 8 w i deba n d i n pu t s p ec tr u m (-f s a m p / 2 t o f s a m p/ 2) s i gn al o f in t e re st a f t e r fr e que nc y t r a n s l a t i o n dc -f s / 1 6 -f s / 8 -3 f s / 1 6 -f s / 4 -5 f s / 1 6 -3 f s / 8 s i g n a l of i n t e r e s t " i m a ge " dc fs / 1 6 fs / 8 3f s / 1 6 fs / 4 5f s / 1 6 3f s / 8 dc -f s / 1 6 -f s / 8 -3 f s / 1 6 -f s / 4 -5 f s / 1 6 -3 f s / 8 fs / 2 -f s / 2 -f s / 2 fs / 2 nco " t u n e s" s i g n al t o w i d e band inpu t s p e c t r um ( e . g . 30 mh z f r o m h i g h s p e e d a d c) f r e que nc y t r ans l a t i on ( e . g . s i ngl e 1 m h z c hann e l t u n e d t o bas ba nd ) figure 2a. a d 6635 frequency translation of wideband input spectrum 1.5 . . . . figure 2b. composite filter respo n se of rcic 2, cic5, and rcf
preliminary technical data AD6635 recommended o p erating condit i ons par a meter temp test lev e l min a d 66 35 bbc ty p ma x units vd d i v 2. 2 5 2. 5 2. 7 5 v vd di o i v 3. 0 3. 3 3. 6 v t ambient i v -4 0 + 2 5 + 7 0 rev. pr b. 7 / 25/2002 7
preliminary technical data AD6635 general timing characte ristics 1, 2 par a meter (conditi ons ) temp test lev e l min a d 66 35 bbc ty p ma x units c l k ti mi n g r e qui re me nt s: t clk c l k pe r i o d f u l l i 1 2 . 5 n s t clkl c l k w i dt h l o w ful l iv 5. 6 0. 5 x t clk n s t clkh c l k w i dt h hi gh ful l iv 5. 6 0. 5 x t clk n s /reset timi ng re quireme n ts: t resl / r e s e t w i d t h l o w f u l l i 3 0 . 0 n s i npu t wid e b and d a t a ti m i ng requ irem en ts: t si inpu t to clk setup tim e ful l i v 2. 0 n s t hi inpu t to clk ho ld tim e ful l i v 1. 0 n s level indic a tor output switching c h aracteri stics: t dli clk to li(a-a,b; b - a,b) ou t p u t delay ti m e ful l i v 3. 3 10 . 0 n s s y nc ti m i ng requ irem en ts: t ss sy nc( a ,b,c, d ) t o c l k s e t up ti m e ful l i v 2. 0 n s t hs sy nc( a ,b,c, d ) t o clk ho ld tim e ful l i v 1. 0 n s seri al p o rt c o nt rol ti mi n g r e qui re me nt s: s w itch i ng c h ara c teristics 2 t sclk s c lk n pe ri o d ful l i v 1 6 n s t sclkl sc lk n l o w t i m e ful l iv 3. 0 ns t sclkh s c lk n hi g h t i m e ful l i v 3. 0 n s inpu t cha r a c teristics: t ssi sdin t o scl k n setup tim e ful l i v 1. 0 n s t hsi sdin t o scl k n hold tim e ful l i v 1. 0 n s par a l l e l port t i mi ng re qui re ment s ( m ast e r mo de) s w itch i ng chara c teristics: 3 t dpocl k l clk to pc lk n d e l a y (di v i d e by 1) ful l i v 6. 5 10 . 5 n s t dpocl k ll clk to pc lk n d e l a y (di v i d e by 2, 4, o r 8 ) ful l i v 8. 3 14 . 6 n s t dpreq clk to p x req delay 1. 0 t dpp c l k t o px [1 5: 0] del a y 0. 0 inpu t cha r a c teristics: t spa px ack t o pcl k n s e tup ti m e 7. 0 t hpa px ack t o p c lkn hold ti m e -3 . 0 par a l l e l port t i mi ng re qui re ment s ( s l a ve mo de) s w itch i ng chara c teristics: 3 t poclk p c l k n pe r i o d f u l l i 1 2 . 5 n s t poclk l pc lk n l o w p e ri o d ( w hen p c lk di vi s o r = 1) ful l iv 2. 0 0. 5* t poclk n s t poclk h pc lk n hi g h p e ri o d ( w hen p c lk di vi s o r = 1) ful l iv 2. 0 0. 5* t poclk n s t dpreq clk to p x req delay 1 0 . 0 t dpp c l k t o px [1 5: 0] del a y 1 1 . 0 inpu t cha r a c teristics: t spa px ack t o pcl k n s e tup ti m e 1. 0 t hpa px ack t o p c lkn hold ti m e 1. 0 li nk p o rt ti mi ng re qui re men t s s w itch i ng chara c teristics: 3 t rdlcl k pclkn to lxcl ko ut d e lay ful l i v 2. 5 n s t fdlcl k pclkn to lxcl ko ut d e lay ful l i v 0 n s t rlclk dat lclkout t o l x [7:0] dela y ful l i v 0 2. 9 n s t flclk dat lclkout t o l x [7:0] dela y ful l i v 0 2. 2 n s not es 1 al l tim i ng s p eci fi cat i ons val i d o v e r vd d r a nge o f 2. 2 5 v t o 2 . 7 5 v a n d vd di o ra nge of 3 . 0 v t o 3. 6 v . 2 (c load =40p f on al l o u t p ut s unl ess ot her w i s e speci fi ed) 3 the t i m i ng pa ram e t e rs for p x [ 1 5: 0] , p x r e q, px ac k , l x c l ko ut, l x [ 7 : 0 ] a ppl y f o r po rt a a n d b . ( x st a nds f o r a or b ) specifications subject t o ch ang e with ou t n o t i ce 8 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 microprocessor port ti m i ng charact eris t i cs 1, 2 a d 66 35 bbc mic r o p r o cesso r po rt, mo de i n m ( m o d e= 0) temp test lev e l m i n t y p m a x units mode in m w r ite timing: t sc c ont r o l 3 to mode in m r e ad timi ng: t sc c ont r o l 3 to a d 66 35 bbc mic r o p r o cesso r po rt, mo de mn m ( m o d e=1) temp test lev e l m i n t y p m a x units mode mnm write timing: t sc c ont r o l 3 to mode mnm read ti ming: t sc c ont r o l 3 to rev. pr b. 7 / 25/2002 9
preliminary technical data AD6635 10 rev. pr b. 7 / 25/2002 absolute maximum ratings 1 supply voltage?????.?????.???.. +3.6v input voltage??????...-0.3 to 5.3v (5v tolerant) output voltage swing????..-0.3v to vddio +0.3v load capacitance???????..?????.200pf junction temperature under bias?..?.???.+125 q c storage temperature range???.......-65 q c to +150 q c lead temperature (5 sec)????..???.?..+280 q c notes 1 stresses greater than those listed a bove may cause permanent damage to the device these are stress ratings only; functional operation of the devices at these or any other conditions greater than those indicated in the operational sections of this specifi cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics 324-lead bga: t ja ==xx q c /watt, no airflow t ja = xx q c/watt, 200-lfpm airflow t ja = xx q c/watt, 400-lfpm airflow thermal measurements made in the horizontal position on a 4-layer board . explanation of test levels i 100% production tested. ii 100% production tested at 25 q c, and sampled tested at specified temperatures. iii sample tested only iv parameter guaranteed by design and analysis v parameter is typical value only vi 100% production tested at 25 q c, and sampled tested at temperature extremes ordering guide model temperature range package description package option AD6635xbc 1 -40 q c to +85 q c (ambient) 324-lead bga (ball grid array) 324 bga AD6635bbc -40 q c to +85 q c (ambient) 324-lead bga (ball grid array) 324 bga AD6635bc/pcb evaluation board with AD6635 and software notes 1 x-grade material is pre-production material, normally shipped during product characterization and qualification. esd sensitivity the AD6635 is an esd (electro static discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD6635 features proprietary esd prot ection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data AD6635 rev. pr b. 7 / 25/2002 11 pin conf igurati o n 19 mm sq. 1.0 mm 19mm x 19m m - 18 2 ball z a pho d packag e - (bottom v i ew) b a l l le ge n d i/o gro und ring pow e r core pow e r no connect 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 a b c d e f g h i j k l m n o p q r
preliminary technical data AD6635 12 rev. pr b. 7 / 25/2002 bal l co nfiguration
preliminary technical data AD6635 rev. pr b. 7 / 25/2002 13 pin functions nam e t y p e functi o n power s u p p ly vd d p 2. 5v s u p p ly vd di o p 3. 3v i o s u ppl y gn d g gr ou n d inp u ts 1 in a[ 13: 0] i a i n put dat a ( m ant i ssa) 1 ex pa [2 :0 ] i a inp u t d a ta (exp on en t) 2 ien a i in p u t ena b le ? in p u t a 1 inb[13 :0 ] i b inpu t data (man tissa) 1 expb[2 :0 ] i b inpu t data (exp on en t) 2 ienb i in p u t ena b le ? in p u t b 1 inc[13 :0 ] i c inpu t data (man tissa) 1 expc[2 :0 ] i c inpu t data (exp on en t) 2 ienc i in p u t ena b le ? in p u t c 1 in d[ 13: 0] i d i n put dat a ( m ant i ssa) 1 ex pd [2 :0 ] i d inp u t d a ta (exp on en t) 2 ien d i in p u t ena b le ? in p u t d /reset i activ e low reset pin clk i i npu t clo c k (master clo c k) pc lk 0 i/ o li nk/ pa ral l e l p o rt c l oc k f o r o u t p ut p o r t s a a n d b pc lk 1 i/ o li nk/ pa ral l e l p o rt c l oc k f o r o u t p ut p o r t s c a n d d lacl ki n i link p o rt a d a ta ready lbclki n i link p o rt b da ta ready lcclki n i link p o rt c da ta ready ldcl ki n i link p o rt d d a ta ready 1 sync a i al l sy nc pi n s go t o al l ei ght out put c h a n n e l s 1 sync b i al l sy nc pi n s go t o al l ei ght out put c h a n n e l s 1 sync c i al l sy nc pi n s go t o al l ei ght out put c h a n n e l s 1 sync d i al l sy nc pi n s go t o al l ei ght out put c h a n n e l s 1 /cs0 i ch ip select fo r ch an n e ls 0 th ro ugh 3 an d ports a and b 1 /cs1 i ch ip select fo r ch an n e ls 4 th ro ugh 7 an d ports c and d 1 c h ip 0_ i d [ 2 : 0 ] i c h i p id sel ect or f o r cha n nel s 0 t h r o ug h 3 a n d po rt s a a n d b 1 c h ip 1_ i d [ 2 : 0 ] i c h i p id sel ect or f o r cha n nel s 4 t h r o ug h 7 a n d po rt s c a n d d co ntr o l paack i parallel port a ack nowledg e pareq o parallel port a requ est pback i parallel po rt b ack n o wle dge pbreq o parallel port b req u e st pcack i parallel po rt c ack n o wle dge pcreq o parallel port c req u e st pdack i parallel port d ack nowledg e pdreq o parallel port d requ est m i cr op ort c o n t ro l d[ 7: 0] i / o / t b i - d irection a l micro p o r t dat a a [ 2 : 0 ] i micr o por t addr ess b u s /ds(/rd) i activ e low data strob e (act iv e lo w read) 2 /dtack(rdy) o/t activ e low data ackno wledg e (micropo rt statu s bit) r/w (/ w r ) i read write ( a ctive lo w writ e ) mode i in tel o r m o toro la m o d e select
preliminary technical data AD6635 pin functions co ntinued nam e t y p e functi o n seri al po r t co ntr o l 1 sd i0 i ser i al po r t c o n t ro l d a ta i nput f o r ch ann e ls 0 thro ugh 3 1 sc lk0 i seri al p o rt c o nt r o l c l ock f o r cha nnel s 0 t h r o u g h 3 1 sd i4 i ser i al po r t c o n t ro l d a ta i nput f o r ch ann e ls 4 thro ugh 7 1 sc lk4 i seri al p o rt c o nt r o l c l ock f o r cha nnel s 4 t h r o u g h 7 outp uts lia - a o level i n di cat or ? i n put a, inte rleave d -data a lia - b o level i n di cat or ? i n put a, inte rleave d -data b lib - a o level i n di cat or ? i n put b, interleave d -data a lib - b o level i n di cat or ? i n put b, interleave d -data b lic - a o level i n di cat or ? i n put c, interleave d -data a lic - b o level i n di cat or ? i n put c, interleave d -data b lid - a o level i n di cat or ? i n put d, inte rleave d -data a lid - b o level i n di cat or ? i n put d, inte rleave d -data b lacl ko ut o link p o rt a cl ock o u tp ut lbclkout o lin k po rt b cl o c k ou tpu t lcclkout o lin k po rt c cl o c k ou tpu t ldcl ko ut o link p o rt d cl ock o u tp ut la[ 7 :0] o link p o rt a o u tp ut data lb[7: 0 ] o link p o rt b output data lc[7: 0 ] o link p o rt c output data ld[ 7 :0] o link p o rt d o u tp ut data pa[15 : 0 ] o parallel ou tpu t data port a pb[15 : 0 ] o parallel ou tpu t data port b pc[15 : 0 ] o parallel ou tpu t data port c pd[15 : 0 ] o parallel ou tpu t data port d pach[1 :0 ] o parallel ou tpu t port a ch annel ind i cator pbch[1 :0 ] o parallel ou tpu t port b c h ann e l ind i cato r pcch[1 :0 ] o parallel ou tpu t port c c h ann e l ind i cato r pdch[1 :0 ] o parallel ou tpu t port d ch annel ind i cator pai q o parallel po rt a i/q data in dic a tor pbiq o parallel po rt b i/q data i n dicator pciq o parallel po rt c i/q data i n dicator pdi q o parallel po rt d i/q data in dic a tor jt a g & b i s t 2 /trst i test reset pin 1 tclk i test clock input 2 tms0 i test mod e sel ect i npu t fo r chan n e ls 0 th roug h 3 2 tms1 i test mod e sel ect i npu t fo r chan n e ls 4 th roug h 7 t d o o / t t e s t d a t a out p u t 2 td i i test d a ta input 1 pi ns wi t h a pu l l - do w n re si st or o f nom i n al 70 k o h m s 2 pi ns wi t h a pu l l - up resi st o r o f nom i n al 70 k ohm s 14 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 timing diagrams lix-y clk t clk t clk h t cl k l t dl i fi gure 3 . leve l in di cat o r out put sw i t c hi n g c har act e ri st i c s. rese t t r esl figure 4. reset timing requir ements sc l k t scl k l t sc l k h fi gure 5 . sc l k sw i t c hi n g c har act e ri st i c s sd i sc l k t ss i da t a n t hs i fi gure 6 . seri al p o rt i n put t i mi ng c h ar act e ri st i c s inx[13:0] expx[2:0] ienx clk t si t hi rev. pr b. 7 / 25/2002 15
preliminary technical data AD6635 fig u r e 7. i npu t tim i ng f o r a an d b c h ann els synca syncb syncc syncd clk t ss t hs fig u r e 8. s y n c tim i ng i npu ts pcl k n cl k t dp o c lk l fi gure 9 . pc l k t o c l k sw i t c hi n g c har act e ri st i c s di vi de by 1 t poc l k l t poc l k l h pcl k n cl k t dp oclkll fi gure 1 0 . pc lk t o c l k sw i t chi n g c h ar act e ri st i c s di vi de by 2, 4, or 8 pc l k n px ack t spa t hp a fi gure 1 1 . m a st er mo de px a c k t o pc lk s e t up a n d h o l d c har act e ri st i c s 16 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 pc l k n px re q pxa c k px[15:0] da ta 1 data 2 t dpp t spa dat a n-1 data n t spa t dpp fi gure 1 2 . m a st er mo de px a c k t o pc lk s w i t c hi ng c h a r act e ri st i c s px re q pxack p x [ 1 5: 0] pcl k n t dpr e q da ta 1 da t a n t dp p t dp p fi gure 1 3 . m a st er mo de px r e q t o pc lk s w i t c hi ng c h a r act e ri st i c s pc l k n px ack t sp a t hpa t po c l k h t po c l kl fi gure 1 4 . sl a ve mo de px ac k t o pc lk set u p a n d hol d c har act e ri st i c s rev. pr b. 7 / 25/2002 17
preliminary technical data AD6635 pc l k n px re q pxa c k px[15:0] da ta 1 data 2 t dpp t spa dat a n-1 data n t spa t dpp fi gure 1 5 . sl a ve mo de px ac k t o pc lk sw i t chi n g c h ar act e ri st i c s px re q pxack p x [ 1 5: 0] pcl k n t dpr e q da ta 1 da t a n t dp p t dp p fi gure 1 6 . sl a ve mo de px re q t o pc lk sw i t c hi ng c h arac t e ri st i c s pclk n lx c l k o ut t f d lclk t rdlc l k fi gure 1 7 . lx c l k o u t t o p c lk sw i t c hi n g c h aract e ri st i c s 18 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 lxclkout lxc l kin lx [7:0] d0 d1 d 2 d3 w a i t >= 6 cy cle s on e t i m e co nne ct i i v i ty che c k d15 8 lx clk o ut c y c l es d0 d1 d 2 d3 d4 n ext t r an s f er be g i ns n ext tr an sf er ackn o w l e d g e fig u r e 18 . lxclkin to lxc l kout da t a s w itch i ng chara c teristics lx cl kout lx[7:0] t fd lcl k da t t rd l c lkd a t fi gure 1 9 . lx c l k o u t t o l x [ 7 :0 ] d at a sw i t c hi ng c h arac t e ri st i c s rev. pr b. 7 / 25/2002 19
preliminary technical data AD6635 timing diagrams ? inm microport mode t sam / rd (/ ds ) /w r ( r w ) /c s0 a [ 2: 0] d[ 7: 0] rdy ( / d t ac k) v a lid a ddres s valid d a ta t sam t ham t ham t drd y t hw r t acc notes : 1. t ac c ac c e s s ti me depends on the addr es s ac c e s s ed. ac c e s s ti me i s meas ur ed fr om f e of /w r to re of rdy. t ac c r equi r e s a max i mum of 9 clk per i ods t sc t hc clk /c s 1 figure 20. inm microport wr ite timing requ iremen ts. t sam / rd (/ ds ) /wr ( r w ) /cs0 a [ 2: 0] d[ 7: 0] rdy ( / d t ac k) va lid ad d r e s s t drdy t ac c va lid d a ta t ha no t e s : 1. t ac c ac c e s s ti me depen ds on the addr es s ac c e s s ed. ac c e s s ti me i s meas ur ed fr om f e o f /w r to re of rdy. t ac c r equi r e s a max i mum of 13 clk per i ods and appl i e s to a[2:0]=7,6,5,3,2,1 t sc t hc clk /cs1 fi gure 2 1 . in m mi cro p o rt r e ad ti mi ng re qui re me nt s. 20 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 timing diagrams ? mnm microport mo de t sam /ds ( / rd ) rw (/ wr ) /cs0 a [ 2: 0] d[ 7: 0 ] /dt a ck (r d y ) va lid ad d r e s s va lid d a ta t sam t ha m t ha m t hr w t ac c t hd s t dd t a c k not e s : 1. t ac c a c c e s s ti me depends on the addr es s ac c e s s e d . ac c e s s ti me i s me as ur ed fr om t he f e of /ds to the f e o f /dt a ck. t a cc r equi r e s a ma x i mum of 9 c l k per i o ds t sc t hc cl k /cs1 figure 22. mn m microport wr ite timing requ iremen ts. t sam / d s (/ rd) rw (/ wr) /c s0 a [ 2: 0] d[ 7: 0] /d tac k (rd y ) valid addr e s s t hds t acc valid d a ta t ha t ddt ack notes : 1. t ac c ac c e s s ti me depends on the addres s ac c e s s ed. ac c e s s ti me i s meas ured from the f e of /d s to the f e of /dt a c k . t ac c requi res a max i mum of 13 clk peri ods t sc t hc clk /c s1 fi gure 2 3 . mn m mi cro p o rt r e ad ti mi ng re qui re me nt s. rev. pr b. 7 / 25/2002 21
preliminary technical data AD6635 input data ports th e ad 663 5 featu r es fo ur h i g h speed ad c in pu t por ts, in pu t ports a, b, c and d. th e inpu t ports allo w for th e m o st flex ib ility with a sing le t u n e r ch ip. th ese can b e di ve rsi t y i n p u t s o r t r ul y i n dep e nde nt i n p u t s s u ch as separat e a n t e n n a se gm ent s . c h an nel s 0 t h r o ug h 3 ca n t a ke d a ta fro m eith er o f t h e inpu t po rts a o r b indep e nd en tly. si m ilarly ch an n e ls 4 throug h 7 can tak e data fro m eith er of th e inp u t po rts c o r d ind e p e nd en tly. for ad ded flex ib ility, each input port can be use d t o support m u ltip lexed i n puts su ch as fo und o n th e ad 6600 o r o t h e r adcs w ith m u l tip lex e d outp u t s. th is add e d flex ib ility can allow for up t o 8 di f f ere n t anal og s o u r c e s t o be pr oces sed si m u ltan e o u s ly b y th e 8 in ternal ch ann e ls. in add itio n, th e fron t end of the ad663 5 con t ain s circu itry th at en ab les h i g h speed sign al lev e l d e tection an d con t ro l. th is is acco m p lish e d with a un iqu e h i gh sp eed lev e l d e tectio n circuit th at o f fers min i m a l laten c y an d m a x i m u m flex ib ility to co n t ro l up to fou r an al o g sign al p a th s. th e ove ral l si g n al pat h l a t e ncy f r o m i nput t o o u t put o n t h e a d 66 35 can be exp r essed in h i gh s p ee d clock cycles. the equat i o n bel o w can be use d t o cal cul a t e t h e l a t e ncy . () 26 7 5 2 + + + = taps cic rcic latency n m m t m rcic2 and m ci c5 are decim a tion val u es for t h e rcic2 and cic5 filters resp ectiv ely, n taps i s t h e num ber r c f t a ps chosen. inpu t da ta f o rmat each i n pu t p o rt co nsists of a 1 4 -b it m a n tissa and 3 - b it exp o n ent. if i n terfacin g t o a s t anda rd a d c i s re qui red , the exp o n ent bi t s c a n be gr o u n d e d . i f c o n n ect e d t o a fl oat i n g poi nt a d c s u c h as t h e a d 6 6 0 0 , t h e n t h e e x po ne nt bi t s fr om t h at pr od uct can be c o n n ect ed t o t h e i n put e x po ne nt b its of th e ad6 635 . th e m a n tissa d a ta fo rmat is two ? s com p l e m e nt and t h e ex p one nt i s u n si g n ed bi n a ry . inpu t timing the data from each high-s pee d input port is latched on the risin g edg e of clk. th is cl ock si g n a l is u s ed to sam p le th e i n p u t p o r t an d cl ock t h e sy nc hr o n o u s si g n al pr ocessi ng stag es th at fo llo w in t h e selec t ed cha n nels. t si t hi clk in[13: 0] ex p [ 2: 0 ] da t a fig u r e 26 . inpu t da ta timi n g requ iremen ts the cl ock signals can operate up to 80 m h z an d h a v e a 50 % dut y cy cl e. in ap pl i cat i ons u s i n g hi g h spee d adc s, th e adc sam p le clo c k or d a ta v a lid strob e is typ i cally use d t o cl oc k t h e ad 6 6 3 5 . t clk t clkl t clkh clk fig u r e 27 . clk tim i ng requirem e n t s inpu t en able contr o l th er e ar e fo ur i npu t en ab le pin s ienx ( x =a, b, c or d ) cor r es po n d i n g t o i n di vi d u al i n put p o rt s a t h r o u g h d. the r e are four m odes of ope ration possible while using each ie n pi n. usi n g t h es e m odes, i t i s p o ssi bl e t o em ul at e ope rat i o n of t h e ot he r r s ps s u ch as t h e ad 6 6 2 0 , w h i c h of fer d u al channel m odes norm ally associated with di versity o p e ration s . these m o d e s are: ien tran sitio n to low, ien tran sitio n to hi g h , ien hi g h an d blank o n ien low. in t h e ie n hi g h m ode, t h e i n put s an d n o rm al ope rat i o ns o ccur wh en th e in pu t en ab le is high . in th e ien tran sitio n t o l o w m ode, no rm al operat i ons o ccu r on t h e fi rst ri si n g ed g e of t h e clock after the ien tran sitio ns t o low. lik e wise i n t h e ien tran sition to hi g h m o d e , op eratio n s occur on the ri sing edge of the clock afte r the ie n tran sitio ns to high . see t h e numeric a lly contr o lled oscilla to r sect i on f o r m o re d e t a i l s on c o nfi g u r i n g t h e i npu t en ab le mo d e s. i n blan k on i e n low m o d e , th e i npu t d a ta is in terpreted as ze ro when ien is low. a typ i cal app l i catio n f o r input m o d e s wo u l d b e to tak e t h e dat a f r om an a d 6 6 0 0 di versi t y adc t o one of t h e i n p u t s of t h e a d 6 6 3 5 . t h e a/ b _ o u t fr om t h at chi p w oul d be tied to the ien. th en o n e ch an n e l with in th e ad663 5 wou l d b e set so th at ien transitio n to low i s en ab led. an ot he r c h a n n e l wo ul d be co nfi g u r ed s o t h a t ien tran sitio n to hi g h is en ab led . th is wou l d allo w two o f t h e a d 66 35 ch an nels to b e co nf igu r ed t o em u l at e th at a d 66 20 i n d i ver s ity m o d e . th oug h th e n c o fr eq u e n c ies and ot her cha n nel cha r acterist i cs woul d need to be set si m ilarl y, bu t th is feat u r e allows the ad6 635 to h a nd le interleave d data stream s such as fo und o n th e ad 660 0. th e d i fferen ce b e tween th e ien tran sitio n to h i gh an d th e ien hi gh i s f o un d w h en a sy s t em cl ock i s pr ovi ded t h at i s h i gh er th an th e d a ta rate of t h e con v e rter. it is o f ten adva nt age o us t o s u p p l y a cl oc k t h at r uns fast er t h a n t h e d a ta rate so t h at ad d ition a l filter tap s can b e co m p u t ed . th is n a turally p r ov id es b e tter filterin g . in o r d e r to en su re t h at ot he r pa rt s o f t h e ci rcui t pr op er ly r ecogn ize the faster clo c k i n the si m p lest man n e r, th e ien tran si tio n to low o r hi g h s h oul d be use d . i n t h i s m ode , onl y t h e fi rst cl oc k 22 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 ed g e th at m eet s th e set u p and ho ld tim es will b e u s ed to l a t c h an d pr oce ss t h e i n p u t dat a . al l ot he r cl ock s pul ses are i g n o re d by fr ont e n d pr oce ssi ng . h o we ve r, eac h cl ock cycle will still p r od u c e a n e w filter co m p u t atio n p a ir. ga in switching the AD6635 includes circ ui t r y th at is u s eful in ap p lication s wh ere eith er la rge dynam i c ranges e x ist or whe r e gain ra nging c o nve r ters are em ployed. t h is circu itry allows d i g ital th resho l d s to b e set su ch th at an up pe r a n d a l o wer t h re sh ol d can be pr o g ra m m e d. one such use of this m a y be t o detect when an adc conve r ter is a b out t o reach ful l -scale with a particular i n put co nd itio n. th e resu lts wou l d b e to pro v i d e a flag th at coul d be use d t o qui c k l y i n ser t an at t e n u at o r t h at w oul d pre v e n t a d c o v er dri v e. i f 18 db (o r a n y ot h e r ar bi t r ary v a lu e) o f attenu atio n (o r g a i n ) is switch e d in, th en th e sig n a l d y n a m i c ran g e of th e syste m will h a ve b e en i n crease d by 1 8 db . the p r o cess be gi n s wh en t h e i n put signal reaches the upper-progr ammed thres h old. in a t y pi cal appl i cat i on, t h i s m a y be set 1 db ( u se r defi na bl e) b e low fu ll-scal e. wh en t h is i n pu t co nd ition is m e t, th e appropriate li signal (lia-a , li b-a , li c- a or li d- a) associated with their c o rres po ndi ng i n put p o r t s a t h ro u g h d is m a d e activ e. th is can b e u s ed t o switch th e g a in or atten u a tion o f t h e ex tern al circu it. th e li line stays activ e u n til th e i n p u t co nd itio n falls b e low th e lower p r o g ramm ed t h res hol d. i n o r de r t o p r ovi de hy st eri s i s , a d w el l t i m e r e g i ster ( s ee me m o r y map fo r in pu t con t ro l reg i ster s) is av ailab l e to hold off switch i ng o f th e con t ro l lin e fo r a p r ed eterm i n e d n u m b e r o f clo c k s . on ce th e i n pu t co nd ition is b e low t h e lower th resho l d, th e pro g ramm a b le coun ter begi ns c o unt i n g hi g h -s pee d cl ock s . as l o ng as t h e i n p u t si gnal st ay s bel o w t h e l o we r t h res h ol d f o r t h e n u m b er o f h i gh -sp e ed clock cycles p r o g ra mm ed , th e atten u a t o r will b e rem o v e d on th e term in al co un t. howev e r, if th e i n pu t co nd itio n go es ab ov e t h e lower thresh o l d with th e coun ter runn ing , it will b e reset an d mu st fall b e low t h e lower th resh o l d ag ain to in itiate th e p r o cess. th is will p r ev en t un - n ecessary s w i t c hi n g bet w e e n st at es. th is is illu strat e d in th e drawi n g b e l o w. wh en th e inp u t si gnal g o es a b ove t h e u ppe r t h res h ol d, t h e a p p r op ri at e li sig n a l b e co m e s activ e. on ce t h e si g n a l falls b e low th e l o we r t h res hol d, t h e c o u n t e r begi ns c o unt i n g. i f t h e i n put co nd itio n go es ab ov e t h e lower thresh o l d , t h e cou n t er is reset and starts again as s h own in the drawi n g below. once the c o unt er has term inat ed to 0, th e li lin e go es in activ e. fi gure 2 8 . t h r e sh ol d set t i ngs f o r l i the l i l i n e can be use d fo r a v a ri et y of f unct i ons . it ca n b e u s ed to set th e co n t ro ls of an attenu ator, dvga o r in te g r a t ed an d u s ed w i th an an a l og v g a . to s i mp lif y th e u s e o f th is featu r e, th e ad6 63 5 in clud es two sep a rate g a i n settin g s , on e wh en th is lin e is in activ e (rcic 2 _quiet[4 :0 ] st ore d i n bi t s 9 : 5 o f 0 x 9 2 regi st er) a n d t h e ot her w h e n act i v e (rc ic 2 _ l ou d [ 4: 0] st o r ed i n bi t s 4: 0 of 0 x 9 2 reg i ster). th is allo ws t h e d i g i tal g a in t o b e ad ju sted to th e ex tern al ch anges. in conj un ct io n with t h e g a in settin g, a v a riab le ho ld-off is in clud ed t o co m p en sate fo r th e p i p e lin e d e lay of th e adc an d th e switch i n g tim e o f th e g a i n cont rol elem ent. t oget h er, these two feat ure s provide seamless g a in switch i ng . ano t h e r u s e of th is p i n is t o facilitate a g a in rang e ho ld o f f wi t h i n a gai n r a ngi ng a d c . for c o n v ert e rs t h at use gai n rang ing t o in crease to tal sign al d y n a m i c ran g e, it m a y b e desi ra bl e t o p r ohi bi t i n t e r n al gai n ra ngi ng f r o m occur r i n g in s o m e instances. for s u c h co nv erters, th e li (a or b) lin e can b e u s ed to ho ld th is off. fo r th is app licatio n , th e up pe r t h res hol d wo ul d be set base d on si m i lar cri t e ri on . ho we ver , t h e l o we r t h res h ol d w oul d be set t o a l e vel co nsisten t with th e g a in ran g e s of th e sp ecific con v e rter. th en th e ho ld o f f d e lay can be set app r op r i ately f o r an y o f a n u m b er o f fa ct ors suc h as fa di n g pr ofi l e , si gnal pea k t o av erag e ratio or an y o t h e r time b a sed ch aracteristics th at might cause un-neces sary gain c h anges . th e ad663 5 has a to tal o f 8 gain con t ro l circu its to sup p o rt al l c h a nnel s an d he nc e can be use d e v en w h e n al l in pu t ports h a ve in terleav ed data. wh en data is in terleav e d on a ce rt ai n i n put p o rt , ap pr o p riate b it shou ld b e set i n gain rang e c o n t ro l reg i ster. th is way bo th in terleav ed chan nel dat a c a n be m oni t o re d a n d li a - b , lib - b , lic - b or li d-b pi ns associ at ed wi t h t h ei r c o r r es po ndi ng i n put ports a through d act as o u t p ut i n di cat or s f o r t h e in terleav ed ch an n e l. lix-a p i n s act as ind i cato rs fo r i n pu t d a ta cor r e spond ing to i e nx l o w and lix - b act as i ndi cat o r s fo r i n p u t dat a co rr e s po n d i n g t o i e nx hi gh i n t h i s m ode. when interleaved cha n nels are not us ed l i x-b pins are c o m p limentary to l i x-a pi ns act i n g as i n di cat ors wi t h o ppo site po lari ty. it shou ld b e no ted t h at th e g a in con t ro l ci rcui t s are wi deba n d a n d are im pl em ent e d pri o r t o a n y filterin g elem e n ts to m i n i miz e lo op d e lay. th e ch ip also prov id es appropriate scalin g of th e in tern al d a ta b a sed on t h e attenu ation asso ciated with th e li si g n a l. in th is m a n n e r, d a ta to th e dsp m a in tain s a co rrect scale v a lu e t h rou ghou t th e pr o cess, mak i n g it t o tally inde pende n t. since the r e oft e n a r e fi nite de lays associated wi t h e x t e r n al g a i n s w i t c hi n g c o m pone nt s, t h e a d 6 6 3 5 include s a vari able pi peline delay that can be use d t o co m p en sate fo r ex tern al p i p e lin e d e lays or g r o ss settling ti m e s asso ciated with g a in /atten u a t o r d e v i ces. th is d e lay m a y be set u p t o 7 hi g h -s pee d cl ocks . t h ese feat ure s ens u re sm oot h swi t c hi n g bet w een gai n set t i ngs. low er th r e s h ol d d w e ll t i m e "h i g h " " low " ti m e ma n t i s s a u ppe r t h res h o l d co u n te r re s t ar ts rev. pr b. 7 / 25/2002 23
preliminary technical data AD6635 inpu t data sc aling the AD6635 has four data input ports. eac h acce pts 14- b it m a n t i s s a ( t w o ? s c o m p le men t in teger ) i n [1 3: 0] , a 3 - bi t exp o n ent ( unsi gne d i n t e ge r ) exp [ 2: 0] an d t h e in p u t en ab le(ien). all fo ur inpu t p o rts are clo c ked b y clk. these pi n s al l o w di rect i n t e rfa ci ng t o bot h st a nda r d fi xed - poi nt adcs s u ch as the ad9225 a n d ad6640, as well as t o gai n - r an gi ng a d c s s u ch as th e a d 66 00 . fo r nor m a l o p e ration with adcs h a v i ng fewer th an 1 4 bits, th e activ e b its shou ld b e msb ju stified an d th e un used lsbs sho u l d be t i e d l o w . th e 3 - b it expon en t, ex p[2 : 0 ] is in terp r e ted as an un sign ed in teg e r. th e ex pon en t will su b s equ e n tly b e m o d i fied b y either of rcic 2 _ l o u d [ 4 :0] o r rc ic2 _ q u i e t [4: 0 ] d e p e nd ing o n wh et h e r li line is activ e o r no t. th ese 5-b it scale values are store d i n rcic2 scale regist er (0x92) a n d th e scaling is ap p lied b e fo re t h e d a ta en ters t h e rcic2 resam p lin g filter. th ese 5-b it re g i sters con t ai n scale v a lu es to co m p en sate for th e rc ic2 gain , ex tern al atten u a tor (if use d ) a n d t h e ex po ne nt o ffs et (ex p o f f ) . i f no ext e rnal atten u a tor is u s ed , bo th t h e rcic2_ quiet an d rc ic 2 _ l o ud regi st ers w o ul d co nt ai n t h e sa m e val u e. a det a i l e d e xpl a n at i on a n d eq uat i on f o r set t i ng t h e at t e nuat i n g sca l e regi st er i s gi ven bel o w i n s cal i ng fo r fl oat i n g- poi nt adc s sect i o n. scaling w i th fixed - poi n t a d c s fo r f i x e d-p o i n t ad cs th e ad6 635 ex pon en t in pu ts, exp [ 2: 0] are t y pi cal l y not us ed a n d s h o u l d be t i e d l o w . th e adc ou tpu t s are tied d i rectly to th e ad6 635 inpu ts, msb-ju stified. th e expo ff b its in 0 x92 sh ould b e pr o g ram m ed t o 0. li kewi se, t h e e x po ne nt i n vert bi t sho u l d be 0. t hus f o r fi xed - p o i n t adc s , t h e ex po ne nt s are typ i cally stat ic an d no i n pu t scalin g is u s ed in th e ad66 35 . AD6635 ad6 640 d1 1 ( m s b ) d0 ( l s b ) in 13 in 2 ex p0 ex p1 in 0 in 1 ex p2 ie n vd d (ex p o f f = 0, e x p i nv = 0) fi gure 2 9 . ty pi cal int e rc o n n ect i on of t h e a d 6 6 4 0 f i xed p o i n t ad c and th e ad6 635 . scaling w i th floa tin g -p oin t o r g a in-r an gin g ad cs an exam ple of the e x ponent c ont rol feature c o m b ines the a d 66 00 and t h e a d 66 35 . th e a d 66 00 is an 1 1 -b it ad c with 3 - b its of gain rang ing . in effect, th e 11 -b it adc p r ov id es t h e man tissa, an d th e 3-b its o f relativ e si g n a l streng th i n d i cato r (rssi) fo r th e ex pon en t. on ly fiv e of the eig h t av ailab l e step s ar e u s ed b y th e ad 6600 . see t h e ad66 00 d a ta sh eet fo r add ition a l d e tails. fo r gain -r an g i n g ad cs su ch as th e ad 660 0, ) 8 , 2 7 mod( 2 _ rcic exp in input scaled + ? ? ? = , ex pi nv = 1, expw ei g h t =0 whe r e: i n i s t h e val u e o f in [ 1 3: 0] , e x p i s t h e val u e of ex p[ 2:0] , a n d rc ic2 is the rcic s cale re g i ster v a lu e (0 x92 b its 9- 5 and 4- 0) . th e rssi ou tpu t of t h e a d 660 0 nu m e r i cally gr ow s w ith in cr easing signal str e ng th of t h e an alog input ( r ssi = 5 f o r a large signal, rssi= 0 for a s m all signal). whe n t h e ex po ne nt i nve rt b i t (ex p i n v ) i s set t o ze r o , t h e ad 6 6 3 5 will co nsid er t h e sm allest sig n a l at th e in[13 : 0 ] to b e th e largest a n d as t h e e x p word i n creases, it sh ifts th e d a ta d o wn in tern all y (exp = 5 will sh ift an 1 4 b i t wo rd righ t b y 5 in tern al b its b e fo re p a ssing th e d a ta t o t h e rcic2). in this exam ple where expinv =0, th e ad 663 5 reg a rd s t h e larg est si g n a l po ssib l e on th e ad66 00 as th e sm al lest si gnal . t h u s , we ca n use t h e ex po ne nt i nve rt b i t t o m a ke the AD6635 e x pone nt agree w ith th e ad66 00 rssi. by settin g ex pin v =1 , t h is forces th e ad6 635 to sh ift t h e d a ta up (l eft ) f o r gr owi n g e x p i n s t ead o f d o w n . the e x po ne nt in v e rt b it sh ou l d always b e set h i gh fo r u s e with th e a d 66 00 . the e x po ne nt of fset i s use d t o s h i f t t h e dat a u p . f o r exam ple, tabl e 2_1 s h ows t h at with n o rc ic2 scaling , 12 d b o f ran g e is lo st wh en th e adc i n pu t is at th e larg est lev e l. th is is un d e sired b ecause th is lowers t h e dyn a m i c r a nge an d sn r of t h e sy st em by reduci n g t h e si g n al of in terest relative to th e qu an tizatio n n o i se fl oo r. to avo i d t h is au to m a tic atten u atio n of t h e full-scale adc sig n a l t h e expoff is u s ed to m o v e th e larg est sig n a l (rssi = 5 ) up t o t h e poi nt w h e r e t h ere i s no d o w n shi f t . i n ot he r wo rd s, o n ce t h e ex p one nt i n v e rt bi t has bee n set , t h e ex po ne nt o ffs et sh oul d be a d ju st ed s o t h at m od(7- 5 + exp o f f ,8) = 0 . th is is th e case wh en ex ponen t of fset is set to 6 sin c e m o d ( 8 , 8 ) = 0 . tab l e 2 _ 2 illu strates th e u s e of ex pi nv an d ex po ff w h e n use d wi t h t h e a d 6 6 0 0 adc . 24 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 ad c inp u t level a d 66 00 r ssi[2 :0 ] a d 66 35 dat a signal red ucti o n large s t 10 1 ( 5 ) / 4 (>> 2 ) -1 2 db 10 0 ( 4 ) /8 (>> 3 ) -1 8 db 01 1 ( 3 ) / 16 (>> 4) -2 4 db 01 0 ( 2 ) / 32 (>> 5) -3 0 db 00 1 ( 1 ) / 64 (>> 6) -3 6 db smallest 00 0 ( 0 ) / 1 2 8 (>> 7 ) -4 2 db numeri c all y co ntrol l e d oscillator frequenc y tr anslation th is p r o cessi ng stag e co m p rises a d i g ital tun e r con s isting o f two m u ltip li ers an d a 3 2 -b it co m p lex nc o. each chan nel of t h e ad 6 6 3 5 has a n i n de pen d e n t nc o. t h e nco serv es as a qu ad rat u re l o cal oscillato r cap ab le of pr o duci n g a n c o f r e que ncy bet w ee n ?c lk / 2 an d +c l k / 2 with a reso lu ti o n of clk/2 32 in th e co m p lex m o d e . th e worst-case sp uriou s si g n a l from th e nc o is b e tter th an - 10 0 d b c f o r al l out put fre q u en ci es. e x pin v = 1 , r c ic 2 scal e = 0) ta bl e 2 _ 1 . a d 66 0 0 t r ansf e r f unct i o n w i t h a d 6 6 3 5 ex pi nv = 1 , an d no exp o ff. th e n c o fr equ e n c y v a lu e in r e g i ster s 0x8 5 an d 0x8 6 ar e in terpreted as a 32 -b it un sign ed in teg e r. th e nco fre que ncy i s ca l c ul at ed usi n g t h e e quat i o n bel o w . ad c inp u t level a d 66 00 r ssi[2 :0 ] a d 66 35 dat a signal red ucti o n large s t 10 1 ( 5 ) / 1 (>> 0) -0 db 10 0 ( 4 ) / 2 (>> 1) -6 db 01 1 ( 3 ) / 4 (>> 2) -1 2 db 01 0 ( 2 ) / 8 (>> 3) -1 8 db 00 1 ( 1 ) / 16 (>> 4 ) -2 4 db smallest 00 0 ( 0 ) / 32 (>> 5 ) -3 0 db ) mod( * 2 _ 32 clk f freq nco channel = wh ere, nc o_freq is th e 32 -b it in teg e r (registers 0 x 8 5 an d 0x 86) , f channel i s t h e desi re d c h a n n el f r eq uency a n d clk is th e ad6 635 ma ster clo ck ra te o r inpu t da ta ra te d e p e nd ing o n th e i npu t enab le mo d e used. see in pu t en abl e m o de c ont r o l sect i o n bel o w . (e xpi n v = 1, e x po ff = 6, e x pwei gh t = 0) nc o fre quen c y h o l d -of f r e gi ster whe n t h e nc o f r eq ue ncy r e gi st ers a r e wri t t e n, dat a i s act ual l y passe d t o a sha d ow re gi st er. dat a m a y be m oved t o t h e m a i n re g i st ers by o n e of t w o m e t hods. whe n t h e channel c o m e s out of slee p m ode o r w h en a sy nc h o p o ccurs. in eith er ev en t a coun ter can b e lo ad ed with nco fre que ncy hol d - o f f regi st er val u e. t h e 16 - b i t u n si g n e d i n t e ger co u n t e r ( 0 x 8 4 ) st a r t s c o u n t i n g do w n cl ocke d by t h e master cloc k a n d whe n it reac hes ze ro the ne w freque ncy v a lu e i n the shad ow reg i ster i s written to t h e nco fre que ncy re gi st er. t h e nc o coul d al s o be s e t up t o s y nc i mmed i ately in wh ich case th e frequ e n c y hold -o ff co un ter i s by pass ed an d new fr eq ue n c y val u es are u pdat e d immediately. tab l e 2_2 . ad 660 0 tran sfer fu n c tion with ad6 620 expi nv = 1, a n d ex p o f f = 6. th is flex ib ility in h a nd ling t h e exp o n e n t allows the AD6635 t o int e rface with ot her gain ranging adcs besi des t h e a d 6 6 0 0 . t h e e x po ne nt o f f s et can be a d j u st e d t o al l o w u p t o 7 r s s i ( e x p ) r a nge s t o be use d as o p pose d to th e ad660 0s 5 . it also allows the ad6 635 to b e tailo red i n a syste m th at e m p l o y s th e ad6 600 b u t do es no t u tilize all o f its sign al ran g e . fo r ex am p l e if o n l y th e first 4 r s s i ra nges are e xpect e d t o occ u r t h e n t h e ex p o f f c oul d be a d j u st e d t o 5 whi c h wo ul d t h en m a ke r ssi = 4 cor r es po n d t o t h e 0 db poi nt of t h e a d 6 6 3 5 . p h a s e of f s et the phase offs et register (0x87) adds a n offs et to the phase accum u lator of the nco. t h i s is a 16-bit re gister a n d is in terpreted as a 16 -b it un sign ed in teg e r. a 0x 000 0 in t h is register corres p onds t o a 0 r a dian offset a n d a 0xffff corres ponds to an of fset of 2 d1 0 ( m s b ) d0 ( l s b ) in 13 in 1 ex p0 ex p1 in 0 ex p2 ad 66 00 ad 66 35 in 2 rssi 2 rssi 1 rssi 0 ab_ o u t i en nc o co ntr o l regis t er th e nco con t ro l reg i ster lo cated at 0x8 8 is u s ed to configure the features of th e n c o . th e s e ar e co n t ro lle d on a per cha n n e l basi s. t h ese are desc ri be d bel o w. fi gure 3 0 . ty p i cal i n t e rco n n e c t i on of t h e ad 66 0 0 gai n- ra ng i n g ad c a n d t h e ad6 635 . rev. pr b. 7 / 25/2002 25
preliminary technical data AD6635 by-p ass the nco in t h e front end of t h e AD6635 ca n be by- p a ssed . by-pass m o d e is en ab led b y setting b it 0 of 0 x88 hi g h . whe n n c o i s by - p asse d, d o w n c o nve rsi o n i s n o t per f o r m e d an d t h e a d 6 6 3 5 c h annel f unct i o ns si m p l y as a real filter o n com p lex d a ta. th is is u s efu l for b a se-b an d sam p ling application whe r e t h e a input is c o nnected to t h e i sign al p a th with in th e filter an d th e b inp u t is conn ected to th e q sign al p a th . th is m a y b e d e sired if th e d i g itized si gnal has al re ady bee n c o nv ert e d t o base- b and i n p r i o r anal o g st a g es o r by ot her di gi t a l pre - p r ocessi ng . phase di ther th e ad663 5 prov id es a p h a se d ith er o p tion for im p r ov ing t h e s p u r i o us pe rf orm a nce o f t h e nco. phas e dithe r is enabl e d by set t i ng bi t 1 . wh e n pha se di t h er i s ena b l e d by set t i ng t h i s bi t hi g h , sp ur s due t o pha se t r unc at i on i n t h e nco a r e ra ndomized. t h e e n ergy from these spurs is sprea d i n t o t h e noi se fl o o r a n d sp uri o us f r ee dy nam i c r a nge i s i n c r e a sed at t h e e x p e nse of ve ry sl i ght dec r eases in the snr . t h e c hoice of whet h e r ph ase dith er is u s ed in a syste m will u lti mately b e d e cid e d b y th e sy ste m g o a ls. if l o we r s p u r s a r e desi re d at t h e expe nse o f a sl i ght l y rai s e d noi se fl o o r , i t s h o u l d be em pl oy ed. if a l o w noi se fl o o r i s d e sired an d th e h i gh er sp urs ca n b e to lerated o r filtered b y subseque nt sta g es, the n phas e dith er is n o t need ed. amplitude dither am pl i t ude di t h er can al so be use d t o i m pro v e s p uri o us per f o r m a nce of t h e nc o . am pl i t ude di t h e r i s ena b l e d by set t i ng bi t 2. am pl i t ude di t h er i m proves p e rf orm a nce by rando m i z i n g the am p litu d e quan tizatio n erro rs with i n th e an gu lar to cartesian co nv ersio n of t h e nco. th is o p tion m a y reduce sp urs at t h e e x pe nse of a sl i g ht l y rai s ed n o i s e floo r. am p litu d e dith er and ph ase dith er can b e u s ed t oget h e r , sepa r a t e l y or not at al l . clear phase accumulator on hop whe n bit 3 is s e t, the nco phase accum u lator is cleare d p r i o r t o a f r e quen c y hop . th is en su res a consisten t ph ase of the nco on each hop. th e nco phase offset is un- effected b y t h i s settin g and is still in effect. if ph ase cont i n u o u s ho p p i n g i s desi re d, t h i s bi t sh oul d be cl ea red an d th e last phase in t h e nco ph ase reg i ster will b e th e in itiatin g po in t fo r t h e n e w freq u e n c y. inpu t en able contr o l there are f o u r di ffe re nt m odes o f ope rat i o n f o r t h e i n p u t en ab le. each of th e h i g h -sp e ed inpu t ports inclu d e s an ien lin e. an y o f th e four f ilter ch ann e ls 0 throug h 3 can be pr o g ram m ed t o t a ke dat a f r om ei t h er o f t h e t w o a o r b in pu t ports (see wb in put s e lect b e l o w) . si m i lar l y an y of th e fou r filter ch ann e ls 4 t h rou g h 7 can b e prog ramm ed to t a ke dat a f r om ei t h er of t h e t w o c or d i n put po rt s. al o n g with d a ta is th e ienx sign al. each filter ch an n e l can b e con f i g ure d t o p r oces s t h e ie n si gnal i n one o f f o ur m odes. three of t h e mode s are ass o ciated with whe n data is p r o cessed b a sed o n a tim e d i v i sio n m u ltip lex e d d a ta stream . the fourt h m ode is u s ed in app licatio n s th at em pl oy t i m e di vi si o n du pl ex s u ch as rada r, s ona r, ul t r aso u n d an d com m uni cat i ons t h at i n vol ve tdd . mode 00: blank on ie n l o w in th is m o d e , data is b l ank e d wh ile th e ien l i n e is low. during t h e p e ri o d of tim e wh en th e ien line is h i gh , n e w data is strobed on each rising edge of t h e input cloc k. whe n t h e ien line is lowere d, input data is replaced with zero val u es. d u ri ng t h i s peri o d , t h e nc o co nt i nue s t o r u n su ch th at wh en th e ien lin e is raised agai n, t h e nco val u e will b e at t h e valu e it wo u l d hav e o t h e rwise b een in h a d t h e ie n l i n e ne ver bee n l o we r e d. t h i s m ode has t h e e ffect o f b l an k i n g th e d i g ital inpu ts wh en t h e ien lin e is lowered . back en d pro c essin g (rcic 2 , cic5 and rcf) co n tinu e s wh ile th e ien l i n e is h i gh . this m o d e is u s efu l fo r ti m e d i v i sion m u ltip lex e d app licatio n s . mode 01: cl ock on ie n hi gh in th is m o d e , data is clo c k e d i n to t h e ch ip wh ile th e ien lin e is h i g h . du ri n g th e p e ri od o f ti m e wh en th e ien lin e is high, ne w da ta is strobe d on each rising e d ge of the i n put clo c k . wh en ien lin e is lowered, inpu t d a t a is no l o ng er l a t c hed i n t o t h e cha nnel . ad di t i onal l y , nc o a dva nces are hal t e d. h o wev e r, bac k e n d p r ocessi n g (rc ic 2, c i c 5 an d r c f ) c ont i n ue s d u ri ng t h i s pe ri o d . the p r i m ary use f o r th is m o d e is to allo w for a cl ock th at is faster th an th e i n p u t sam p le d a ta rate to allow m o re filter tap s to b e co m p u t ed t h an w oul d ot h e rwi s e be p o ssi bl e. i n t h e di a g ram bel o w, in pu t d a ta is stro b e d on ly du ri n g th e p e riod of tim e wh ile ien is h i gh d e sp ite th e fact that th e clk co ntin u e s t o run at a rate 4 tim e s faster th an the d a ta. nn + 1 cl k ie n in [ 1 3 : 0 ] e [ 2: 0] t si t hi fig u r e 31 . fra c tio na l ra te in pu t ti ming (4x clk) in mo de 0 1 . mo de 10 : cl o c k o n ie n tr a n sition t o hi gh in th is m o d e , data is clo c k e d i n to t h e ch ip only o n t h e first clo c k edg e after th e rising transitio n o f t h e ien lin e. alth oug h d a ta is on ly latch e d o n th e first v a lid clo c k edg e , t h e bac k e n d pr ocessi n g (rc ic 2, c i c 5 an d r c f) c ont i n ues on each availa ble cloc k t h at may be present , sim i lar to mode 01. t h e nco phase ac cum u lator is increm ented onl y once f o r e ach new i n put dat a sam p l e an d not o n ce fo r each input cloc k. mo de 11 : cl o c k o n ie n tr a n sition t o l o w in th is m o d e , data is clo c k e d i n to t h e ch ip only o n t h e first clo c k edg e after th e falling tr an sitio n of th e ien lin e. 26 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 alth oug h d a ta is on ly latch e d o n th e first v a lid clo c k edg e , t h e bac k e n d pr ocessi n g (rc ic 2, c i c 5 an d r c f) c ont i n ues one each available cloc k t h at may be present , sim i lar to mode 01. t h e nco phase ac cum u lator is increm ented onl y once f o r e ach new i n put dat a sam p l e an d not o n ce fo r each input cloc k. r e -sam pl i ng i s im pl em ent e d by ap pa rent l y i n creasi n g t h e in pu t sam p le rate b y th e factor l, using zero stu f fing for th e n e w d a ta sam p les. fo llowin g t h e re-sam p l er is a secon d ord e r cascad ed in teg r ato r co m b filter. filter ch aracteristics are d e term in ed on ly b y th e fractio n a l rate- change (l/m). wb input select th e filter can pro cess sign als at th e fu ll rate o f th e i n pu t po rt 80 m h z. the o u t p ut rat e o f t h i s st age i s gi ve n by t h e equat i o n bel o w . bit 6 in t h is reg i ster co n t ro ls wh ich inpu t port is selected fo r si gnal pr oc essi ng . f o r c h a nnel s 0 t h r o ug h 3 i f t h i s bi t i s set hig h , the n i n p u t po rt b (i nb, e x pb an d ie nb) is co nn ected to the selected filter ch an n e l. if t h i s b it is cleared, the n input port a (ina, expa a n d iena) a r e co nn ected to the selected f ilter ch an n e l. sim i l a rly for chan nel s 4 t h r o ug h 7 i n p u t po r t d i s sel ect e d whe n bi t 6 i s set and inpu t po rt c is selected wh en t h is b it is cleared. 2 2 2 rcic samp rcic samp m f l f = sync select bits 7 and 8 of th is reg i ster d e termin e wh ich ex tern al syn c pin is ass o ciated with the se le cted cha n nel. th e ad 663 5 has fo u r sy nc p i ns nam e d sy nc a, s ync b , s ync c , an d sy ncd. any of these sy nc p i ns ca n be ass o ciated with any of t h e eight receive r c h an nels within t h e AD6635. ad di t i onal l y , i f onl y one sy nc si g n al i s re q u i r ed f o r t h e sy st em , al l 8 re cei ver c h a nnel s can re fere nce t h e sam e sy nc pulse . bit val u e 00 selects s y nc a, 01 selec t s sync b, 10 selects sync c a n d 11 s e lects sync d. th e frequ en cy respon se o f th e rcic 2 filter is g i v e n b y th e fo llowing equ a tio n s . 2 1 2 1 1 2 1 ) ( 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? z z l z h rcic rcic rcic l m rcic s 2 2 2 2 sin sin 2 1 ) ( 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = samp samp rcic rcic rcic s f f f l f m l f h rcic 2 nd order rcic filter the rcic 2 filt er is a second order cascade d re-sam pling in teg r ator c o mb filter. th e resam p ler is i m p l e m en ted usi n g a u n i q ue t echni q u e, w h i c h doe s not req u i r e t h e use of a hi g h - spee d cl ock , t h us si m p li fy i ng t h e desi gn an d savi ng po we r. the re -sam pler allow s f o r n o n - inte g e r rel a t i ons hi ps b e t w een t h e m a st er cl oc k a n d t h e out put dat a rate. th is allows easier im p l e m en tatio n o f syste m s th at are eith er m u lti- mo d e or requ ire a m a ster clo c k th at is no t a m u l tip le o f t h e d a ta rate t o b e u s ed . the scale factor, s rcic2 i s a p r og ram m abl e unsi g ne d 5 bi t bet w ee n 0 a n d 31 . thi s ser v e s as a n at t e n u at or t h at ca n reduce t h e gain of the rcic 2 i n 6db increm ents. for t h e best dy nam i c range , s rcic2 s h oul d be set t o t h e sm al l e st v a lu e po ssib l e (i.e. l o west atten u a tion) with ou t creating an ove rfl ow co n d i t i on. thi s c a n be sa fel y acc om pl i s hed usi n g t h e e quat i on bel o w, w h e r e input_level is th e larg est fraction of full-scale possi ble at th e inp u t to t h e ad66 35 (norm a lly 1). the rcic 2 scal e factor is al wa ys use d whet her o r not t h e rc ic 2 i s by passe d. i n terpo l atio n up to 512 an d deci m a tio n up t o 4 096 is allo wed in t h e rcic2. th e re -sam pling fact or for the rcic2 (l) is a 9 - b it in teg e r. wh en co m b in ed with th e deci m a ti on fac t or m , a 12 - b i t num ber, t h e t o t a l rat e -c han g e can b e an y fractio n in th e fo rm o f : more ove r, there are t w o scale re gisters ( r c i c 2_ loud[ 4 : 0 ] b its 4 - 0 in x 92) , and (rc ic 2 _ q u i e t[4: 0] bi t s 9- 5 i n x 9 2 ) w h i c h are used i n co nju n c tion wi th th e co m p u t ed s rcic2 wh ich d e term in es th e ove ral l rc ic 2 scal i ng. t h e s rcic2 val u e m u st be s u m m ed with the val u es in eac h respe c tive scale re gis t ers and expoff to dete rm ine the scale value that m u st be placed in the rc ic2 scale re gister. thi s num b er m u st be less t h an 32 or t h e i n t e rp ol a t i on a n d deci m a t i on rat e s m u st be a d j u st e d to v a lid ate th is eq u a tion . th e ceil fun c tio n den o t es th e next w hol e i n t e ger an d t h e fl oo r fu nct i o n de not es t h e pre v i o us w hol e i n t e ge r. f o r e x am pl e, t h e cei l ( 4. 5) i s 5 wh ile th e fl o o r(4.5) is 4 . m l r rcic = rcic r th e on ly con s train t is th at th e ratio l/m m u st b e less t h an o r equ a l to on e. th is im p lies th at th e rcic 2 d ecim a tes b y 1 or m o re. rev. pr b. 7 / 25/2002 27
preliminary technical data AD6635 28 rev. pr b. 7 / 25/2002 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? + = rcic rcic rcic rcic rcic rcic rcic rcic l m floor l m l m floor m ceil s ( ) level input s l m ol rcic rcic rcic cic _ 2 2 2 2 2 2 ? ? = exam ple calc ulati o ns go al: im p l e m en t a filter with an in pu t sam p le rate o f 1 0 m h z r e qu ir i n g 100 d b of alias rej ectio n fo r a +/- 7k h z pass ban d . so lu tion : first d e term in e th e p e rcen tag e of t h e sam p le rate t h at i s re prese n t e d by t h e pass ba nd . 0 , 2 _ ) 8 , 2 mod( = ? = + ? expinv in input scaled rcic exp 1 , 2 _ ) 8 , 2 7 mod( = ? = + ? ? expinv in input scaled rcic exp 07 . 0 10 7 * 100 = = mhz khz bw fraction whe r e: i n i s t h e val u e o f in [ 1 5: 0] , e x p i s t h e val u e o f ex p[ 2 : 0 ] , an d r c i c 2 is th e v a lu e of t h e 0 x92 (rc ic 2 _ q u i e t[4: 0] an d rc i c 2_l o u d [ 4: 0 ] ) scal e register . fin d th e -1 00db co lu m n on t h e r i gh t of the tab l e and l o ok d o wn th is co l u m n f o r a v a l u e g r eater th an o r eq u a l t o your pass ban d pe rce n t a ge o f t h e cl ock rat e . t h e n l o o k ac r o ss t o the ext r em e left colum n and find the c o rres p onding rate change factor (m rcic2 /l rc ic2 ). referri ng to t h e table, notice th at fo r a m rcic2 /l rcic2 of 4, t h e fre q u ency ha vi n g -1 0 0db o f alias rej ectio n is 0 . 0 7 1 p e rcen t, wh ich is slig h tly g r eater than t h e 0.07 percent calc u la ted . th erefore, for th is exam ple, the maxim u m bound on rcic2 rate change is 4. a higher chose n m rcic2 /l rcic2 mean s less alias rej ectio n t h an t h e 10 0 d b re qui re d. rcic2 re jecti o n the ta ble 3 bel o w illustrates t h e am ount of bandwidt h in p e rcen t o f t h e d a ta rate i n to t h e rcic2 stag e. th e d a ta in th is tab l e m a y b e scaled to any o t h e r allowab l e sam p le rate up t o 8 0 m h z i n si ngl e c h a n nel m o de or 4 0 m h z i n di ve rsi t y c h an nel m o de. t h e t a bl e ca n be u s ed as a t o ol t o deci de ho w t o di st ri b u t e t h e deci m a t i on be t w een rc ic 2, cic5 and th e rcf. an m rcic2 /l rci c 2 o f less th an 4 wou l d still yi eld th e req u i r e d reject i o n , ho we ver , t h e po we r c ons um pt i on ca n b e m i nim i zed by deci m a ti ng as m u ch as possi ble in this rcic2 stage . decim a tion in rcic2 lo wers the data rate, and t h us red u c e s p o w e r c o ns um ed i n s ubse que nt st a g es. i t sho u l d al so be not e d t h at t h er e i s m o re t h a n one way t o get t h e deci m a t i on by 4. a deci m a t i on o f 4 i s t h e sam e as an l/ m rat i o of 0. 25 . th us a n y i n t e ge r c o m b i n at i on of l/ m th at yield s 0.25 will wo rk (1 / 4 , 2 / 8 o r 4 / 1 6 ). howev e r, for t h e be st dy nam i c ran g e, t h e si m p l e st rat i o sh oul d be use d . for e x am pl e, ? gi ve s bet t e r per f o r m a nce t h an 4/ 1 6 . m rcic2 /l rcic2 - 50d b - 60d b - 70d b - 80d b - 90d b - 100 d b 2 1. 7 9 1. 00 7 0 . 56 6 0. 31 8 0 . 17 9 0. 10 1 3 1. 50 8 0. 85 8 0 . 48 6 0. 27 4 0 . 15 5 0. 08 7 4 1. 21 7 0. 69 6 0 . 39 5 0. 22 3 0 . 12 6 0. 07 1 5 1. 00 6 0. 57 7 0 . 32 8 0. 18 6 0 . 10 5 0. 05 9 6 0. 85 3 0. 4 9 0. 27 9 0 . 15 8 0. 08 9 0 . 0 5 7 0. 73 9 0. 42 5 0 . 24 2 0. 13 7 0 . 07 7 0. 04 4 8 0. 65 1 0. 37 4 0 . 21 3 0. 12 1 0. 03 8 9 0. 58 1 0. 33 4 0 . 1 9 0. 10 8 0 . 06 1 0. 03 4 1 0 0. 52 5 0. 30 2 0 . 17 2 0. 09 7 0 . 05 5 0. 03 1 1 1 0. 47 8 0. 27 5 0 . 15 7 0. 08 9 0 . 0 5 0. 02 8 1 2 0. 43 9 0. 25 3 0 . 14 4 0. 08 2 0 . 04 6 0. 02 6 1 3 0. 40 6 0. 23 4 0 . 13 3 0. 07 5 0 . 04 3 0. 02 4 1 4 0 . 37 8 0. 21 7 0. 12 4 0. 0 7 0. 0 4 0. 02 2 1 5 0. 35 3 0. 20 3 0 . 11 6 0. 06 6 0 . 03 7 0. 02 1 1 6 0. 33 1 0. 1 9 0. 10 9 0 . 06 1 0. 03 5 0 . 0 2 0 . 06 8 decimation and int erpolati o n re gisters rc ic 2 deci m a ti on val u e s are st ore d i n re gi st er 0x 9 0 . thi s regi st er i s a 12 -bi t re gi st er an d c ont ai n s t h e deci m a ti on p o rtion less 1 . th e i n terpo l atio n portio n is st o r ed i n reg i ster 0x9 1. th is 9 - b it v a l u e ho ld s th e i n terpo l atio n less one . rcic 2 scal e reg i ster 0 x92 co n t ains th e scalin g info rm ati o n fo r th is sectio n o f th e circu it. th e pr imary fun c tion is to store t h e scale value com puted in t h e s ections a b ove . ta bl e 3 . ss b r c ic 2 al i a s rej ect i on t a bl e ( f samp = 1) ba ndw i d t h s h o w n i n perce n t a ge of f samp.
preliminary technical data AD6635 b i t s 4- 0 ( r c i c 2 _ l o u d [ 4: 0] ) o f t h i s re gi st er are use d t o co n t ain th e scalin g facto r fo r t h e rcic2 during co nd itio ns of strong si gna ls. t h ese 5 bits re prese n t the rcic2 scalar calculated a b ove plus any e x t e rnal si gnal sc aling with a n atten u a tor. b i t s 9- 5 ( r c i c 2 _ q uie t [ 4 : 0 ] ) of th is r e g i s t er a r e us e d to co n t ain th e scalin g facto r fo r t h e rcic2 during co nd itio ns o f weak si g n a l s . in th is reg i st er, no ex tern al atten u a tor would be used and is not i n cluded. only the value com puted a b ove is stored in t h ese bits. bit 1 0 o f th is reg i ster is u s ed to ind i cate th e v a lu e of th e ex tern al expo nen t . if th is b it is set low, then each external exponent re pre s ents 6 db per step a s in t h e ad66 00 . if t h is b it is set to high, each exp o n e n t represe n ts a 12 db ste p . bit 1 1 o f th is reg i ster is u s ed to inv e rt t h e extern al exp o n ent be fo r e i n t e r n al cal cu l a t i on. thi s bi t sh oul d be set high fo r g a i n rang ing adcs th at u s e an in creasin g ex pon en t t o rep r esen t an in creasin g sign al l e v e l. th is b it sho u l d be set l o w f o r gai n ra ngi ng a d c s t h at use a decreasi n g expone nt for repre s en ting an in creasin g sign al lev e l. in app licatio n s th at do no t re quire t h e fe ature s of the rcic2, it m a y b e b y settin g the l/m ratio t o 1 / 1 . th is effectively bypasses all circui t r y of th e r c i c 2 ex cep t th e scalin g wh ich i s still effectu a l. 5 th orde r cic filt er the t h ird signa l processi ng stage, c i c5, im ple m ents a sh arp e r fi x e d-co efficien t, d eci matin g filter than rcic2. th e i n pu t rate to th is filter is f samp2 . the m a xi m u m i nput rat e i s gi ven by t h e e quat i on b e l o w. n ch equals tw o fo r di ve rsi t y c h an nel r eal i n put m ode; ot her w i s e n ch e qual s one . i n or der t o sat i s fy t h i s e quat i o n, m rcic2 can be increase d , n ch can be re duce d , o r f clk ca n be increase d (re fere nce fract i onal rat e i n put t i m i ng desc ri b e d i n t h e ?inpu t tim i n g ? sectio n). ch clk samp n f f hz z z s m ci c ci c () =? ? ? ? ? ? ? ? ? + ? ? hf mf f f f s ci c samp samp cic () sin sin =? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ( ) ( ) ? ? = cic cic cic ol m ceil s ( ) ol m s ol ci c ci c ci c ci c 5 5 5 5 2 2 5 =? + th e ou tpu t rate of th is stag e is g i v e n b y th e eq u a tion bel o w. f f m sa m p sa m p ci c 5 2 5 = cic 5 re jecti o n the ta ble 4 bel o w illustrates t h e am ount of bandwidt h in perce n t a ge o f t h e cl oc k rat e t h at can be pr ot e c t e d wi t h v a ri o u s d ecim a tio n rates and alias rej ection sp ecificatio ns. th e m a x i m u m in pu t rate i n to t h e cic 5 is 80mhz wh en t h e rc ic 2 deci m a tes by 1. a s i n the pre v ious ta ble, the s e are th e ? b a ndwidth ch aracteristics of th e cic 5 . no tice th at the cic 5 stage can protect a m u ch wide r ba nd to a n y give n rej ection . m cic5 - 50d b - 60d b - 70d b - 80d b - 90d b - 100 d b 2 10 .2 2 7 8. 07 8 6 . 39 3 5 . 06 6 4 . 00 8 3 . 18 3 3 7. 92 4 6 . 36 7 5 . 1 1 4. 10 7 3 . 29 7 2 . 64 2 4 6. 21 3 5 . 02 2 4 . 05 7 3 . 27 1 2 . 63 6 2 . 12 1 5 5. 06 8 4 . 10 7 3 . 32 6 2 . 68 7 2 . 1 7 1. 74 8 6 4. 26 7 3 . 46 3 2 . 80 8 2 . 2 7 1. 83 6 1 . 4 8 7 3. 6 8 2. 98 9 2 . 42 5 1 . 96 2 1 . 58 8 1 . 28 1 8 3. 23 3 2 . 62 7 2 . 13 3 1 . 72 6 1 . 39 7 1 . 12 8 9 2. 88 1 2 . 34 2 1 . 90 2 1 . 5 4 1. 24 7 1 . 00 7 1 0 2. 59 8 2 . 11 3 1 . 71 6 1 . 3 9 1. 12 5 0 . 90 9 1 1 2. 36 5 1 . 92 4 1 . 56 3 1 . 26 6 1 . 02 5 0 . 82 8 1 2 2. 1 7 1. 76 5 1 . 43 5 1 . 16 2 0 . 94 1 0 . 7 6 rev. pr b. 7 / 25/2002 29
preliminary technical data AD6635 1 3 2. 00 5 1 . 63 1 1 . 32 6 1 . 07 4 0 . 8 7 0. 70 3 1 4 1. 86 3 1 . 51 6 1 . 23 2 0 . 99 8 0 . 80 9 0 . 65 3 1 5 1. 7 4 1. 41 6 1 . 15 1 0 . 93 2 0 . 75 5 0 . 6 1 1 6 1. 63 2 1 . 32 8 1 . 07 9 0 . 87 4 0 . 70 8 0 . 57 2 1 7 1. 53 6 1 . 2 5 1. 01 6 0 . 82 3 0 . 66 7 0 . 53 9 1 8 1. 45 1 1 . 18 1 0 . 9 6 0. 77 8 0 . 6 3 0. 50 9 1 9 1. 37 5 1 . 11 9 0 . 9 1 0. 73 7 0 . 59 7 0 . 48 3 2 0 1. 30 7 1 . 06 4 0 . 86 5 0 . 70 1 0 . 56 8 0 . 45 9 2 1 1. 24 5 1 . 01 3 0 . 82 4 0 . 66 7 0 . 54 1 0 . 43 7 2 2 1. 18 8 0 . 96 7 0 . 78 6 0 . 63 7 0 . 51 6 0 . 41 7 2 3 1. 13 7 0 . 92 5 0 . 75 2 0 . 6 1 0. 49 4 0 . 39 9 2 4 1. 0 9 0. 88 7 0 . 72 1 0 . 58 4 0 . 47 4 0 . 38 3 2 5 1. 04 6 0 . 85 2 0 . 69 2 0 . 56 1 0 . 45 5 0 . 36 7 2 6 1. 00 6 0 . 81 9 0 . 66 6 0 . 5 4 0. 43 7 0 . 35 3 2 7 0. 96 9 0 . 78 9 0 . 64 1 0 . 5 2 0. 42 1 0 . 3 4 2 8 0. 93 4 0 . 76 1 0 . 61 8 0 . 50 1 0 . 40 6 0 . 32 8 2 9 0. 90 2 0 . 73 4 0 . 59 7 0 . 48 4 0 . 39 2 0 . 31 7 3 0 0. 87 2 0 . 7 1 0. 57 7 0 . 46 8 0 . 37 9 0 . 30 6 3 1 0. 84 4 0 . 68 7 0 . 55 9 0 . 45 3 0 . 36 7 0 . 29 7 3 2 0. 81 8 0 . 66 6 0 . 54 1 0 . 43 9 0 . 35 5 0 . 28 7 ta bl e 4 . s s b c i c 5 al i a s rej ect i on t a bl e ( f samp2 = 1) thi s t a bl e hel p s t o cal c u l a t e an up pe r bo u n d on deci m a ti on, m cic5 , g i v e n th e d e sired filter ch aracteristics. ram coe fficient filte r the fi nal si gna l pr ocessi ng st age i s a sum - of -p ro d u ct s d ecim a t i n g filter with p r o g rammab l e co effi cien ts. a sim p l i f i e d bl oc k di ag ram i s show n bel o w. t h e dat a me m o ries i-r am and q-ram store the 160 m o st recent co m p lex sam p l e s fro m th e prev iou s filter stag e with 2 0 -b it resol u tion. the coe fficient m e m o ry, cmem , stores up to 2 5 6 co efficien t s with 20 -b it reso lu tion . on ev ery clk cy cl e one t a p f o r i a n d one t a p fo r q a r e cal cul a t e d usi n g th e sam e co effi cien ts. th e r c f ou tpu t co n s ists o f 24 b it d a ta b its. 160x 20b i- r a m 256x 20b c- r a m 1 60x 2 0 b q- r a m i i n q i n q o u t i o u t fig u r e 32 . ram co efficien t filter blo ck di a g r am rcf de cima tion re gister each rcf cha nnel ca n be use d to decim a te the data rate. the decim a tion register is an 8 bit re gister a n d can d ecim a te fro m 1 to 256 . th e rcf d ecim a tio n is st o r ed i n 0 x a0 in th e fo rm o f m rcf -1 . th e i n pu t rate to th e rcf is f samp5 . rcf de cimation phase the r c f deci m a t i on p h ase c a n be use d t o s y nch r o n i ze m u l tip le filters with in a ch ip. th is is u s efu l wh en u s i n g m u l tip le ch annels with in th e ad66 35 t o imp l em en t p o l y- p h a se filter all o wi n g th e resou r ces of sev e ral filters to b e p a ralleled . in su ch an ap p licatio n , t w o rcf filters wou l d be pr ocessi ng t h e sam e dat a f r o m t h e c i c 5 . ho we ver , each filter will be delayed by one hal f the de ci m a tion rate, t hus creat i n g a 18 0 - de gree p h a se di f f ere n ce bet w ee n t h e two h a lv es. th e ad66 35 filter ch ann e l u s es th e v a lu e sto r ed in th is reg i ster to pre-l o ad th e rcf co un ter. there f ore i n st e a d of st art i n g f r om 0, t h e c o u n t e r i s l o ade d with th is v a l u e, th us creating an o f fset in th e p r o cessi n g t h at sh o u l d be equi val e nt t o t h e req u i r e d pr o cessi ng del a y . th is d a ta is stored in 0x a1 as an 8 - b it nu m b er. rcf filter le ngt h th e m a x i m u m n u m b e r o f tap s th is filter can calcu late, n taps , i s gi ve n b y t h e eq uat i o n bel o w. t h e va l u e n taps -1 is written t o th e ch ann e l reg i ster with in th e ad6 635 at ad dr ess 0xa 2. ? ? ? ? ? ? ? ? ? samp rcf clk taps f m f n the rcf coe f ficients are l o ca ted in add r esses 0x 00 t o 0 x 7 f and are i n terp reted as 20 -b it 2?s co m p le m e n t n u m b e rs. wh en writing th e co efficien t ram, th e l o wer ad dresses will b e m u ltip lied by relativ ely o l der d a ta fro m th e cic 5 an d th e h i gh er co efficien t add r esses will b e m u l tip lied b y relativ ely n e wer d a ta fro m th e cic5 . th e coefficients ne ed not be sy mmetric and t h e coefficient l e ngt h , n taps , may be e v en or odd. if the c o e f ficients are sym m et ri c, t h e n bot h si des of t h e i m pul se res p o n se m u st b e written i n to th e co efficien t ram. a lth oug h th e base m e m o r y f o r co eff i cien ts i s on ly 128 words long , t h e actu a l leng th is 25 6 wo rd s l o n g . th ere are t w o pa ges, eac h of 1 2 8 w o rds l o n g . t h e pa g e i s sel ect ed b y b it 8 o f 0xa4 . althou gh t h is d a ta m u st b e written in page s, t h e inte rnal core ha ndle s filters that exceed the len g t h of 12 8 tap s . th er ef or e, th e fu ll len g t h of th e d a ta ram m a y b e u s ed as t h e filter leng th (1 60 t a p s ). th e rcf stores th e d a ta fro m th e cic 5 in t o a 16 0x4 0 ra m. 16 0x2 0 is assign ed to i d a ta and 16 0x 20 is assign ed to q d a ta. th e rcf u s es th e ram as a circ ular buffer, s o th at it is d i fficult to kn ow i n w h i c h a d dres s a part i c ul a r d a ta elem en t is sto r ed . to avo i d start-u p tran sien ts du e to 30 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 un de fi ne d dat a r a m val u es , t h e dat a r a m s h o u l d be cleared up on i n itializatio n . wh en t h e rcf is trigg e red t o calcu late a filter o u t p u t , it st art s by m u l t i pl y i ng t h e ol de st val u e i n t h e dat a r a m by th e first co efficien t, wh ich is po in ted to b y t h e rcf coefficient offset register (0 xa 3) . thi s val u e i s accum u lated with the product s of newe r data words m u l tip lied b y t h e sub s equ e n t lo catio n s in t h e co efficien t ram un til th e co efficien t ad dress rcf off +n taps -1 is reache d . coe fficien t addres s impulse resp onse da ta 0 h ( 0 ) n( 0) ol dest 1 h ( 1 ) n( 1 ) 2 = ( n taps - 1 ) h( 2) n( 2) ne west tab l e 5. three-tap filter the rcf coe f ficient offset re gi st er ca n be use d f o r t w o pu r poses . the m a i n pu r pose of t h i s regi st er i s al l o w fo r m u l tip le filters to lo ad ed i n to me m o ry an d selected sim p ly b y ch ang i ng the offset as a p o in ter for rap i d filter ch ang e s. the ot he r use of t h i s regi st er i s t o f o rm part of sy m bol ti min g adj u stmen t . if th e d e si red filter leng t h is p a d d e d with ze ros on t h e e n ds, t h en the starting poi n t can be ad ju sted to fo rm sl ig h t d e lays in wh en t h e filter is com puted with refe re nce to the high-spee d cl ock. this al l o ws fo r ver n i e r ad j u st m e nt of t h e sy m bol t i m i ng. course a d just m e nts can be m a de with t h e rcf decim a tion phase . th e ou tpu t rate of th is filter is d e term in ed b y th e ou tpu t r a te of th e ci c5 s t ag e an d m rcf . rcf samp sampr m f f 5 = rcf ou tp ut scale f a ctor and contr o l re gister register 0xa4 is a com p ound register and is use d to configure se ve ral aspects of t h e rcf re gister. bits 3-0 a r e use d t o set t h e scal e of t h e fi x e d- p o i n t out put m ode. t h i s scal e val u e m a y al so be used t o set t h e fl oat i n g - poi nt out put s i n c o nj unct i o n wi t h bi t 6 of t h i s regi s t er. b i t s 4 an d 5 de t e rm i n e t h e out put m ode. m o de 00 set s t h e ch ip up in fi x e d - po in t m o d e . th e nu m b er of b its is d e term in ed b y th e p a rallel or l i n k po rt con f igu r ation . m ode 0 1 sel ect s fl oat i n g - p o i n t m ode 8+ 4. i n t h i s m ode, a n 8 - b it m a n tissa is fo llowed b y a 4-b it ex pon en t. in m o d e 1 x (x i s d o n ?t ca re ), t h e m ode i s 12+ 4, o r 1 2 bi t m a nt i ssa and 4- bi t ex p one nt . fl oat i n g p o i n t 12 + 4 1x flo a tin g po in t 8 + 4 0 1 fi xed p o i n t 00 ta bl e 6 . o u t p ut m ode fo rm at s norm all y , th e ad66 35 will determin e th e ex pon en t v a lue that optimizes num erical accur acy. howe ver, if bit 6 of th is con t ro l register is set, the v a lu e sto r ed i n b its 3-0 is u s ed to scale the ou tpu t . th is en su res th at con s isten t scalin g and accu r acy du ring co nd itio ns th at may warran t pre d i c t a bl e out put ra nges . if bi t 3 - 0 i s re pre s ent e d by r c f scale, the n t h e scaling factor i n db is give n by: ( ) db scale rcf factor scaling ) 2 ( log 20 * 3 10 ? = rev. pr b. 7 / 25/2002 31
preliminary technical data AD6635 d a ta in tern al to th e ad66 35 al lo ws t h e u s ag e o f m u ltip le channels t o process a si ngle ca rrier. th e snr of the in terp o l ating h a lfb a nd is arou nd ?1 49 .6 d b . th e h i g h e st erro r sp urs du e to fi x e d-po i n t arith m e tic ar e arou nd ?1 72 .9 d b . th e c o efficients of t h e 13-tap i n t e rp ol at i n g h a l f ba nd fir ar e gi ve n i n t h e t a bl e 7 . interpolating h a lf band filters th e ad 6635 h a s four i n terp o l at ing h a l f b a nd f i n ite im p u l se respon se filters th at imm e d i ately preced e t h e four d i g ital agcs and immed i ately fo llow t h e rcf ch an nel ou t p u t s. eac h i n t e rp ol at i n g hal f ba n d t a k e s 1 6 - b i t i a n d 1 6 - bi t q dat a f r o m th e pr eceding rc f and outpu ts 16- b i t i and 16-b it q t o th e ag c . th e h a l f b a nd and ag c op er ate indep e nd en tly o f each other, so t h e agc ca n be bypass e d, in whi c h case t h e ou tpu t of th e h a lf b a nd is sen t directly t o t h e ou t p u t d a ta port. th e h a lf b a nd s also o p er ate i ndep e nd en t of each o t h e r ? an y o n e ca n be e n a b l e d o r di s a bl e d usi n g t h e h a l f b a n d co nt r o l re giste r s. 0 14 0 -6 6 0 30 9 51 2 30 9 0 -6 6 0 14 0 halfb a nd filters also p e rfo r m th e fun c tio n of in terleav ing dat a f r om vari ous r c f c h a n nel o u t p ut s pri o r t o t h e act ual fu nct i o n of i n t e rp ol at i o n . t h i s i n t e rl eavi n g of dat a i s allo wed ev en wh en t h e actual fun c tion o f halfb a n d filter is b y p a ssed . th is feature allows for th e usag e of m u ltip le ch ann e ls (im p l e m e n tin g a po l y p h a se filter) on th e ad6 635 to process a single carrier. e i t h er r c f phase deci m a t i on of start ho ld-off co un ter fo r th e ch ann e ls are u s ed to appropriately phase t h e c h annels. for e x am ple if 2 ch ann e ls o f ad 663 5 ar e u s ed to pro cess one cd ma20 00 carrier, rcf filters fo r bo th the ch an n e ls shou ld b e 18 0 out o f phase . t h i s ca n be do n e usi n g r c f p h ase deci m a ti on or an a p p r op ri at e start ho ld-off co un ter fol l o we d by ap pr o p ri at e nc o phase offsets. tab l e 7. ha lfba n d c o efficien t s automatic gain control th e ad663 5 is equ i pp ed with fou r ind e p e nd en t au to m a tic g a in con t ro l (agc) l o op s fo r d i rect in terface with a rake receiver. eac h agc ci rcuit ha s 96db of range. it is i m p o r tan t t h at th e d ecim a tin g filters o f t h e ad663 5 prece ding t h e agc re ject undesire d si gnals , so that eac h agc l o op is on ly op erating on th e carrier of in terest an d carri ers at ot he r f r e que nci e s d o not a ffect t h e ra ngi ng o f th e loo p . hal f ba nd a ca n l i s t e n t o c h an nel s 0 t o 3: c h a nnel s 0 , 1, 2, and 3; c h a nnel 0 a n d 1; o r onl y chan nel 0. h a l f ba n d b can l i s t e n t o c h annel s 2 an d 3, or o n l y cha n ne l 2. eac h hal f b a nd i n terleav es th e ch an n e ls sp ecified in its co n t ro l register. t h e i n terleaved data so co m b in ed is in terp o l ated by 2 . the i n t e r l eavi n g f u nct i o n ca n be use d i nde pe nde nt o f th e i n terpo l atin g fun c tion , i n wh ich case th e halfb a nd filter is b y p a ssed u s ing t h e halfb a n d con t ro l reg i sters. wh en t h e halfb a nd filter is byp assed th e i n terleav ing fun c tion is still p e rfo r m e d . for o n e ch ann e l ru nn ing at t w i ce t h e c h i p rat e , t h e hal f ba nd can be u s ed t o out put channel data at 4x the chi p rate. the a g c com p ress es t h e 2 3 - bi t com p l e x ou t put fr om t h e in terpo l atin g half b a nd filter i n to a pro g rammab l e word size o f 4-8 , 10 , 12 o r 16 b its. sin ce th e sm all sign als fr o m t h e l o wer bi t s a r e pus he d i n t o hi g h e r bi t s by addi ng gai n , th e clip p i ng o f th e lower b its d o e s n o t co m p ro m i se th e snr o f th e sign al of i n terest. th e agc m a i n tain s a co nstan t m ean p o wer o n th e ou tpu t d e sp ite t h e lev e l of th e sig n a l o f in terest, allo wi n g operatio n in env i ro n m en ts whe r e t h e dyna mic range of t h e signal excee ds the dy nam i c range o f t h e o u t p ut r e sol u t i o n. th e frequ en cy respon se o f th e in terp o l ating halfb a n d fir is sho w n i n th e graph with resp ect to t h e ch ip rate. 0 0.5 1 1.5 2 2.5 3 3.5 4 80 70 60 50 40 30 20 10 0 spectrum of halfband multiples of chip rate db c 0 80 ? () () ? fi gure 3 3 . i n t e rpol at i n g hal f ba n d fre q uenc y resp o n se th e agc and t h e in terpo l ation filters are no t tied tog e th er an d an y on e o r bo th of th em can be selected without the ot he r. t h e a g c sect i on ca n b e by pa ssed i f d e si red, by set t i ng bi t 0 o f t h e a g c c o nt r o l w o rd . whe n by pa ssed t h e i/q d a ta is still clip p e d to a d e sired nu m b er of b its and a con s t a nt gai n c a n be pr o v i d e d t h r o ug h t h e a g c gai n m u l tip lier. 32 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 t h e r e a r e thr e e s o u r c e s o f er ro r in tro d u c ed by th e ag c f u n c tion : und erf l ow , ov erf l ow, and m o du latio n. un de rfl o w i s c a use d by t r u n c a t i on of bi t s be l o w t h e out put ran g e. ove rfl o w i s ca use d by cl i ppi n g e r r o rs whe n t h e out put signal e x ceeds the out put ra nge . m o dulation e r ror occurs when the output gai n var i es dur ing the r ecep tio n of a data. the desi re d si g n al l e vel s h oul d be set base d on t h e p r ob ab ility d e nsity fu n c tion of th e si g n a l so t h at th e errors due t o u nde rfl o w a n d o v e rfl o w a r e bal a nce d . t h e gai n an d d a m p in g v a lu es of th e loo p fil t er shou ld b e set so t h at th e agc i s fast e n ou g h t o t r ac k l o n g t e rm am pl it ude va ri at i ons of the si gnal t h at m i ght cause excessive unde rflow or ove rfl ow , but s l ow e n ou g h t o avoi d e x cessi v e l o ss o f am pl i t ude i n fo rm ati on due t o t h e m odul at i o n o f t h e si g n al . the agc loop th e agc loo p is im p l e m en ted u s ing a log - lin ear architecture. it contains fo ur b a si c o p erat i o ns : po we r calcu latio n , erro r calcu latio n, lo op filterin g an d g a i n m u l tip licatio n . th e agc can b e co nfigu r ed t o o p e rate in one of th e two m odes: desi re d si g n al l e vel m ode o r desi re d cl i ppi n g l e vel m o d e as set b y b it 4 of ag c co n t r o l wo rd (0 x0a , 0x 12) . the agc adjusts the gain of t h e inc o m i ng data according t o h o w far i t i s fr om a gi ven d e si red si g n al l e vel o r desi re d cl i ppi n g l e vel , depe n d i n g on t h e m ode of o p e rat i o n selected. t w o data pat h s t o the ag c loop are pr ov id ed : one , bef o re t h e cl i ppi n g ci rcui t r y an d one aft e r t h e cl i ppi ng cir c u itr y as show n in f i gu r e 34. fo r d e sired sig n a l level m ode, o n l y t h e i/ q pat h f r o m bef o re t h e cl i p pi n g i s use d . for de si re d c l i ppi n g l e vel m ode , t h e di ffe re nce of t h e i/ q sig n a ls fro m b e fore an d after th e clip p i ng circu itry is used. desi red si gn a l l e vel m o de in th is m o d e o f op eration , th e agc striv e s to m a in tain th e out put si g n al a t a p r o g ram m abl e set l e vel . t h i s m ode of o p e ration is sel ected b y pu tting a v a lu e of zero in b it 4 of a g c con t ro l w o r d (0x 0 a , 0x 12) . fi r s t, t h e lo op f i nd s th e squ a re ( o r p o w e r) o f t h e i n c o m i ng com p l e x dat a si g n al by sq uar i ng i and q an d add i ng t h em . th is op eratio n is im pl em ent e d i n e x p o n ent i a l dom ai n usi n g 2 x ( p owe r of 2 ) . the agc loop has an ave r age and decim a te bloc k. this avera g e a n d de cim a te operation takes place on power sam p l e s and be fo re t h e s qua re r oot o p erat i o n. thi s bl oc k can be pr o g ra m m e d t o ave r a g e 1- 1 6 3 8 4 po wer sam p l e s and the decim a te section ca n b e p r og r a mm e d to upd ate th e a g c on ce ev er y 1- 409 6 samp les. th e lim it atio n o n th e avera g ing operation is t h at th e nu mb e r of av er a g ed po w e r sam p les sh ou ld b e a m u ltip le o f th e d ecim a t i o n v a l u e (1x , 2x, 3x or 4x tim es). the a v era g i n g and decim a tion effectively m e ans t h e agc can ope rat e ov er a v era g ed p o w er o f 1- 1 6 3 8 4 out put sam p les. the c hoice of up dating the agc once eve r y 1- 4 096 sam p les an d op eratin g o n av erag e p o wer facilitates th e im p l e m en t a tio n o f loo p fi lter with sl o w ti m e co n s tan t s, whe r e t h e agc error converges sl owly a n d m a kes i n fre q u ent gai n ad ju st m e nt s. it w oul d al s o be usef ul i n scenari o s where the user wa nt s to kee p the gain scaling con s t a nt ove r a fram e of dat a (o r a st ream of sym bol s). x i q x 2 x po w e r o f 2 'p ' p o le 'r ' d e s i r e d m ean s q u a r e ( i + j q ) + lo g 2 (x ) i q c lip c lip 23 bi t s p r ogr am m abl e bi t w i dt h - - () ? ? + ? + ? ? z p z k () ? ? ? + ? ? z z p z k er r o r 'k ' g a in u s ed onl y f o r de s i r e d c l i ppi ng l e v e l m ode a ver age 1 - 16384 sa m p l e s d eci m a t e 1 - 4096 sam p l es g a in m u lt i p li e r s q uar e r o ot fig u r e 34: block d i ag ram o f th e ag c du e to t h e lim i t atio n on t h e nu m b er of a v era g e sam p les to b e a m u ltip le of d ecim a tio n valu e, o n l y t h e m u l tip le num ber 1, 2 , 3 or 4 i s p r og ram m e d. t h i s n u m b er i s p r og r a mm ed in b its 1 , 0 o f 0x 10 an d 0x1 8 r e gister s. th ese avera g e d sam p les are the n d e ci m a ted with deci m a tio n rat i o s pr o g ram m a bl e fr om 1 t o 40 9 6 . thi s d ecim a t i on rat i o is d e f i n e d in 12 -b it r e g i ster s 0 x11 an d 0x1 9. the a v era g e and decim a te opera t i ons are t i e d t oget h er an d i m p l e m en ted usin g a fi rst-o r der cic filter and so m e fifo registers . t h ere is a gain a n d bit growth ass o ciated with cic filters an d th ese d e p e nd o n th e d ecim a t i o n ratio . to com p ensate for the gain a ssoci ated with these operations atten u a tion scalin g is p r ov id ed b e fo re th e c i c filter. this scaling operation accounts for t h e divisi on ass o ciated with av erag ing op eration as well as th e trad itio n a l b it g r o w t h i n cic filters. si n ce this scalin g is imp l em en ted as a b it sh ift op eratio n o n l y co arse scalin g is p o ssib l e. fi n e scale is im plemented as a n offset i n the request level ex p l ain e d later. th e attenu atio n scaling s cic is pr o g ram m abl e fr om 0 t o 14 u s i ng 4 - bi t s of 0 x 1 0 an d 0 x 1 8 regi st ers an d i s gi ve n by : )] * ( [log 2 avg cic cic n m ceil s = rev. pr b. 7 / 25/2002 33
preliminary technical data AD6635 atten u a tion is i m p l e m en ted as a b it sh ift o p eratio n , on ly m u lt i p l e s of 6 . 02 db at t e n u at i ons are p o ssi bl e. s cic in t h is case is 12 cor r espo nd ing t o 72 .2 4d b. th is w a y s cic scaling always atten u a tes m o re th an su fficien t to com p en sate for th e g a in ch an ge s in av e r ag e an d d e c i ma te s e c tio n s and h e n c e prev en t o v e rfl o w s in the agc loop . b u t it is also ev id en t th at t h e cic scaling i s ind u c i n g a g a in error (di f fere nce bet w een gai n due t o c i c a n d at t e nuat i o n p r ov id ed ) of up to 6.02d b. th is erro r shou ld b e com p ensat e d f o r i n t h e r e q u e s t si gnal l e vel as ex pl ai ne d bel o w. 2 1 1 ) 1 ( 1 ) ( ? ? ? + + ? = ? ? ? + ? ? + = + = ? ? + + ? + = ? = ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? = = 34 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 th e l o op filter o u t p u t correspo n d s t o t h e si gn al g a i n that is u p d a ted b y t h e agc. since all co m p u t atio n in th e loo p filter is don e in lo g a rith m i c d o main (to t h e b a se 2) o f th e sam p les, th e sig n a l gain is g e n e rated u s ing t h e ex pon en t (po w er of 2 ) of th e loop filter o u t p u t . the gai n m u l t i pl i e r gi ves t h e pr o duct of t h e si gnal gai n with b o t h th e i an d q d a ta en t e ring th e agc sectio n . th is sig n a l gain is ap p lied as a coarse 4 - b it scalin g and t h en a fin e scale 8-b i t m u lt ip lier. hen ce th e app lied sign al g a i n is b e tw een ?4 8.16 d b to 48 .1 3d b in step s of 0 . 0 24d b. in itial v a lu e for si g n a l gain is prog rammab l e u s i n g th e r e g i ster s 0x0 d an d 0x1 5 fo r ag c a and agc b respectively. th e p r od u c ts of th e g a i n m u lti p lier are th e agc scaled out put s ha ve 1 9 - b i t re prese n t a t i on. these ar e i n t u r n used as i a n d q for calculating t h e powe r a n d agc error and lo op filtered t o produ ce si g n a l gain fo r n e x t set o f sam p les. these agc scaled ou t p ut s ca n be p r o g ram m ed t o have 4 , 5, 6, 7 , 8, 1 0 , 1 2 , o r 16 bi t wi dt hs usi n g t h e a g c co n t r o l wo rd (0 x0a , 0x 12) . the agc scal ed out puts are t r u n cat ed t o re qui red bi t wi dt hs usi n g t h e cl i ppi ng ci rc ui t r y as sh o w n i n t h e bl oc k di ag ra m . open l o op g a in se ttin g : if filter g a i n k o c cu p i es on ly o n e lsb or 0 . 00 39 , th en d u ring th e m u ltip lic atio n with err o r t e rm , erro rs of u p t o 6. 02 db c oul d be t r uncat e d . thi s trun catio n is du e to th e l o wer b it wi d t h s av ai lab l e in t h e agc l o op. if filter g a in k were th e m a x i m u m v a lu e, tr un cated er rors wo u l d b e a less th an 0 . 0 94db ( e qu iv alen t to 1 lsb of error term represen tatio n). generally a sm al l filter g a i n is u s ed to ach iev e a larg e ti m e co nstan t loo p (o r slo w l o o p s ), but in th is case it wo uld cau se la rge er ro rs t o g o und etected . du e th is p e cu liarity, th e d e sign ers recomm end that if a user wa nts slow agc l o ops t h ey rath er use fai r ly h i gh v a lu es fo r filter g a in k and th en u s e cic d ecim a tio n to ach iev e a slo w l o o p . in t h is way th e agc l o op will m a k e larg e infrequ e n t g a i n ch ang e s com p ared t o s m all and fre q uent gai n c h a n ges as in the ca s e o f no rm al s m al l g a in l o op filter. howev e r thou gh t h e agc lo op m a k e s larg e infrequ en t gain ch ang e s a slo w tim e co nstan t is still ach iev e d and t h ere is lesser tru n cation of errors . aver age sam p les setting: t h ough it is com p licated to express the e x a c t effect of the num ber of ave r aging sam p les, th in k i n g in tu itiv ely i t h a s a sm o o t h i n g effect on the way t h e agc loop attacks a s u dde n inc r ease or a spi k e in th e sign al lev e l. if av erag i n g o f 4 sam p les is u s ed , t h e agc will attack a sudd en in crease in si g n a l lev e l m o re s l o w ly co mp a r e d to no av er ag i ng. t h e sam e wo ul d ap pl y to th e m a n n e r i n wh ich th e agc wou l d attack a sudd en decrease in t h e signal level. desired clipping lev e l mode as note d pre v i ously, each agc ca n be c o nfigure d s o t h at t h e l o op l o c k s on t o a de si red cl i ppi n g l e vel or a desi re d si gnal l e vel . t h e desi re d c l i ppi ng le vel m ode can be sel ect ed by set t i ng t h e bi t 4 o f i ndi vi dual a g c co nt rol words (0x0a, 0x12). for signa ls that tend to exceed the bo u nds o f t h e peak -t o - ave r a g e rat i o , desi red cl i ppi n g l e vel opt i o n al l o ws a way t o kee p fr om t r uncat i n g t hos e si g n al s an d still p r o v i de an agc th at attack s qu ick l y and settles to t h e de si red o u t put l e vel . t h e si gnal pat h f o r t h i s m ode o f ope rat i o n i s s h ow n wi t h b r o k e n a r r o w s i n t h e bl oc k d i agram an d the op eration is si m i lar to th e d e sired sign al l e vel m ode. first, th e d a ta fro m th e g a i n mu ltip lier is tru n cated to a l o we r re sol u t i o n (4 , 5, 6, 7 , 8, 10 , 12 , or 1 6 bi t s ) as set by the a g c c o ntr o l w o rd . a n er ro r term (b oth i a n d q ) is gene rat e d t h at i s t h e di ffe ren c e bet w ee n t h e s i gnal s bef o re an d after tru n c atio n . th is term is p a ssed to th e co m p lex squ a re d m a gni t ude bl ock , fo r avera g i n g a n d deci m a ti ng th e upd ate samp les an d tak i ng th eir squ a re roo t to find rms sam p les as in desire d si gnal le vel m o de. in place of th e requ est d e sired sign al level, a d e sired clip p i n g lev e l is subt ract ed, l e a v i n g a n e r r o r t e rm t o be pr oce ssed by t h e secon d ord e r l o op filter. th e rest of t h e loop op erates t h e sam e way as th e d e sired sign al lev e l m o d e . th is way th e trun catio n error is calcu lated an d the agc l o op operates t o main tain a constan t trun cation erro r lev e l. ap art fro m b it 4 o f th e agc co n t ro l wo rd s, th e o n l y reg i ster settin g ch an g e s co m p ared to t h e desired sign al lev e l m o d e is th at th e desired clip p i ng lev e l is stored in t h e a g c desi r e d le vel r e gi st er s ( 0x0 c, 0 x15 ) in stead of th e requ est si g n a l lev e l (as i n desired si g n al lev e l m ode). sync hroniz ation in scena r ios where agc out pu t is c o nnected to a r a ke receiver, t h e r ake recei ver can sy nchroniz e the a v era g e and update sec tion to update t h e a v era g e power for agc erro r calcu lation an d loo p filtering . th is ex tern al syn c signal sy nchronizes the agc changes to r a ke receive r an d m a k e s sure th at th e agc g a in word do es no t ch ang e ove r a sym bol peri od and he n ce m o re accura te estim a tion. suc h synchronization ca n be accom p lished by setting the app r op ri at e bi t s o f t h e a g c c ont rol regi st e r . wh en t h e ch ann e l co m e s ou t o f sleep , it lo ad s t h e agc hol d of f c o u n t e r val u e a n d st ar t s co unt i n g d o w n , cl oc ke d by t h e m a st e r cl ock. whe n t h is counter reac hes ze ro, the cic filter o f t h e agc starts deci m a tio n and u p d a tes t h e agc l o op filter b a sed on t h e cic d ecim a tio n v a lu e set. furt her w h e n e v er t h e use r wa nt s t o sy nc hr o n i ze t h e st art of deci m a ti on f o r a ne w up dat e s a m p l e an a p pr op ri at e h o l d - o f f v a lu e can be set in ag c h o l d -o ff cou n t er (0x 0 b , 0 x13) an d th e syn c no w b it (b it 3 ) i n th e agc contro l word is set. upo n settin g th is b it th e h o l d - o f f cou n t er v a lu e is co un ted dow n an d a ci c d eci mated v a lu e is u p d a ted on th e coun t of zer o . rev. pr b. 7 / 25/2002 35
preliminary technical data AD6635 alon g with upd atin g a n e w valu e, th e cic filter accum u lator ca n be reset if ini t on sync bit (bit 2) of t h e agc con t ro l word is set. each sy n c will in itiate a n e w syn c sign al u n l ess first sy n c on ly b it (b it 1) of th e agc co n t ro l wo rd is set. if t h is b it i s no t set, ag ain th e h o l d - o f f co un ter is lo aded with th e valu e in th e ho ld-o ff reg i ster to count down a n d repeat t h e sa me process. these additional feature s m a ke the agc sync hronization m o re flexi b le and applicable to varied circum sta n ces. th e c h ann e l b i st is a tho r oug h test of th e selected ad66 35 si g n al p a th. with th i s test m o d e , it is po ssib l e to u s e ex tern ally su pp lied v ect o r s or an in tern al p s eud o - ran d o m genera tor. an er ro r s i gnatu re regist er in the rcf m o n ito rs th e ou tpu t d a ta of the ch an n e l and i s u s ed t o d e term in e if the prop er d a ta ex its th e rcf. if erro rs are det ect ed t h en e ach i n t e rnal bl ock m a y be by passe d a n d anot her t e st ca n be ru n t o deb u g t h e fa ul t . t h e i a n d q p a th s are tested ind e p e nd en tly. th e fo llowin g step s sh ou l d b e fo llowed to p e rform th is test. ad dr esses 0 x 0 a ? 0x 1 1 have been rese r v ed f o r co nf igu r i n g ag c a and add r esses 0x1 2 ? 0x 19 h a v e b een reser v e d f o r c o nfi g u r in g agc b. t h e registe r sp ecification s are d e tailed in the ?mem ory map for out p ut port c o nt r o l r e gi st ers? sect i o n of t h i s dat a s h eet . ? ? ? ? user configurable built in self test (bis t) ? ? ? ? ? ra m bi st th e r a m bist can b e u s ed t o v a lid ate fun c tio n a lity o f the on-chi p r a m. this feat ur e provide s a sim p le pass/fai l test, wh ich will g i v e confid ence th at th e ch an n e l r a m is ope rat i o nal . t h e fol l o wi n g st eps s h oul d be f o l l o we d t o p e rform th is test. ? ? ? ? ? ? ? chip synchroni z ation two typ e s of syn c hron izatio n can b e ach i ev ed with th e AD6635. t h es e are start a n d hop. eac h is describe d in det a i l bel o w. the sy nch r oni zat i on i s acc o m pli s hed wi t h the use of a s h adow re gister a n d a hol d off c o unter. see fig u re 35 b e low for a sim p listic sch e m a t i c o f th e nc o s h ad ow r e g i s t er an d n c o fr eq h o ld -o ff coun te r to u n d e r s tand b a sic o p e r a tion . en ab ling t h e cl ock ( a d 6635 clk) fo r th e ho ld off cou n t er can o c cu r with eith er a ta bl e 8 . b i s t regi st er 0xa 8 ch an nel b i st 36 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 1 . to p r og ram a ch ann e l, it m u st first b e set t o sleep m ode ( b i t hi g h ) ( e xt a d d r ess 3) . al l ap pr o p r i a t e co n t ro l and m e m o ry reg i sters (filter) are t h en lo ad ed . the st art u p da t e hol d of f c o unt e r ( 0 x8 3 ) s h oul d be set to 1 . soft _sy n c (via the m i cro port), or a pi n sy n c ( v i a any of th e fou r ad 663 5 sy n c p i ns a , b, c, and d) . th e fun c tion s th at in clud e sh ad ow reg i sters to allo w syn c hron ization in cl u d e : 2 . set th e sleep bits lo w (ex t add r ess 3). th is en ab les the cha n nel. t h e c h annel m u st the slee p m ode low to activate a cha n nel. please not e that whe n usi n g external addres ses, a p propri ate chip selects s h ould be u s ed for th e d i ff e r en t c h ann e ls. 1. st art 2. ho p (nc o fre que ncy ) i0 i3 1 q0 q3 1 mi c r o r egi st er b0 b1 5 tc enb n c o f r equency u pdat e h o l d o f f c ount er i0 i3 1 q0 q3 1 s hadow r e gi s t er i0 i3 1 q0 q3 1 nc o f r equency r egi s t er to nc o ad 663 4 c l k so f t sy n c e n a b l e pi n sy nc en abl e f r om m i c r op or t sta r t with s o ft sy nc th e ad663 5 in clud es t h e ab ility to syn c h r on ize ch ann e ls or chi p s un de r m i cropr ocess o r c ont r o l . o n e act i on t o synchronize is the start of ch an n e ls or ch ip s. th e start up dat e hol d o ff c o unt er ( 0 x 8 3 ) i n c o n j unct i on wi t h t h e start b it an d syn c b it (ex t ad dress 5) allow th is syn c hron ization . basically th e start upd a te ho l d off co un ter d e lays th e start of a c h an nel ( s ) by i t s val u e (n um ber o f a d 6 6 3 5 c l ks . the fol l o wi n g m e t hod i s use d to syn c h r on ize th e start o f m u l tip le ch an n e ls v i a m i cropr ocess o r c ont r o l . 1. set t h e a p p r op r i at e chan nel s t o sl ee p m ode ( a ha rd reset to t h e ad6 635 reset p i n bring s all 4 chan n e ls up in sleep m ode). 2. note t h at the tim e from whe n the rd y (/dt ack ) pin goe s hi g h t o w h en t h e nc o b e gi ns p r oce ssi n g dat a i s the contents of the start updat e hold off c o unte r(s ) (0x83) + 6 m a ster cloc k cycles. 3 . write th e start upd a te ho l d off c o u n t er(s) (0 x83 ) to the appropriate value (great er th an 1 and less th an 2 ^ 16 -1 ). if th e ch ip(s) is n o t i n itialized , all oth e r registers s h oul d be loa d e d at t h is step. fi gure 3 5 . n c o sh a dow reg i st er an d h o l d of f c o unt er the fo u r pi n_ s y nc avai l a bl e o n t h e a d 66 3 5 a r e c o m m on to th e co m p lete ch ip i.e all 8 ch ann e ls and all 4 agcs. on t h e ot her ha n d t h e f o ur so ft s y nc cha n nel s s h are d by chan nel s 0 t o 3 an d agc s a a n d b are di ffe r e nt f r om t h e fo ur s o ft _sy n c cha nnel s sha r e d by cha n nel s 4 t o 7 an d agcs c and d. t h is is the effect of usi n g di ffere n t chi p selects (/cs0 a n d /cs1 ) fo r th ese differe n t se ts of sync chan nel s . it s h oul d be not e d t h at t h ou g h t h e y have t h e sam e nam e s sync a, sy nc b, sy ncc a n d s y ncd t h e two s e ts of sync cha nnels are diffe re nt from each othe r. 4 . write th e start b it and th e sync b it h i gh (ex t ad dr ess 5) . 5 . th is starts th e start upd a te ho ld off c o u n t er cou n t i n g do w n . t h e c o unt er i s cl oc ked wi t h t h e AD6635 cl k signal. whe n i t reaches a c ount of one th e sleep b it o f th e ap pro p riate ch an n e l ( s) is set lo w to activate the c h annel ( s). 6. please note tha t channels 0 t o 3 a n d 4 to 7 wi ll receive sy nc?s d u ri ng di ffe re nt m i cropo rt wri t e s ( s e p arat e sy ncs have t o b e use d fo r c h a n nel s 0 t o 3 an d 4 t o 7 ) . so t h is tim e differe nce (sepa r a t e m i croport writes) sho u l d be not e d fo r t h e t w o s e t s of cha n nel s . start st art re fers t o t h e st art - u p of a n i n di vi dual ch annel , chi p , o r m u l tip le ch ip s. if a ch an n e l is no t used, it sho u l d b e p u t i n th e sleep mode to r e du ce pow er d i ssi p a tio n. fo llow i ng a h a rd reset (l o w pu lse o n th e ad663 5 /reset p i n ) , all channels a r e pl aced in the sle e p m ode . c h a nnels m a y also b e m a n u a lly pu t to sleep b y writing to th e m o d e reg i ster co n t ro lling th e sleep fun c tion . start with pin s y nc th e ad 663 5 has 4 syn c p i n s a , b, c an d d th at can b e use d to provide for ve ry accurate sync hronization chan nel s . eac h c h an nel ca n be pr o g ram m ed t o l o ok at a n y o f th e 4 sy n c pin s . ad d ition a lly, an y or all ch ann e ls can m oni t o r a si n g l e sy nc pi n o r e ach ca n m oni t o r a se pa rat e p i n , pro v i d i ng co m p lete flex ib ility o f syn c hro n i zation . sy nch r oni zat i o n of st art wi t h one o f t h e e x t e rnal si gnal i s accom p lished with the following m e thod. start with no sync if no synchron i zatio n is n e ed ed to start m u lti p l e ch ann e ls or m u ltiple AD6635s, t h e fo ll owi n g m e thod shoul d be u s ed to in itiali ze th e d e v i ce. 1. set t h e a p p r op r i at e chan nel s t o sl ee p m ode ( a ha rd reset to t h e ad6 635 reset p i n bring s all 4 chan n e ls up in sleep m ode). rev. pr b. 7 / 25/2002 37
preliminary technical data AD6635 4 . write th e hop b it and th e sync(s) b it h i gh (ex t ad dr ess 4) . 2. not e t h at t h e t i m e from whe n t h e s ync pi n goe s hi g h t o w h e n t h e n c o b e gi ns pr o cessi ng dat a i s t h e cont e n t s of t h e st art u p dat e h o l d o ff c o unt e r(s ) (0x83) + 3 m a ster cloc k cycles. 5 . th is starts th e nco freq ho ld off co un ter co un ting do w n . t h e c o unt e r i s cl oc ke d wi t h t h e a d 6 6 3 5 c l k signal. whe n i t reaches a c ount of one the new freq u e n c y is l o ad ed in to th e nco. 3 . write th e start upd a te ho l d off c o u n t er(s) (0 x83 ) to the appropriate value (great er th an 1 and less th an 2 ^ 16 -1 ). if t h e ch ip(s) is no t i n itialized , all oth e r registers s h oul d be loa d e d at t h is step. 7. please note tha t channels 0 t o 3 a n d 4 to 7 wi ll receive sy nc?s d u ri ng di ffe re nt m i cropo rt wri t e s ( s e p arat e sy ncs have t o b e use d fo r c h a n nel s 0 t o 3 an d 4 t o 7 ) . so t h is tim e differe nce (sepa r a t e m i croport writes) sho u l d be not e d fo r t h e t w o s e t s of cha n nel s . 4 . set th e start on pin syn c b it an d th e app r op ri ate syn c pi n e n a b l e hi g h (ext a d d r ess 4 ) (a , b , c o r d) . 5. whe n t h e sy nc pi n i s sam p l e d hi g h by t h e a d 6 6 3 5 clk this ena b l e s the c o unt down of t h e start update ho l d off c o unter. th e co un ter is clo c k e d with th e AD6635 cl k signal. whe n i t reaches a c ount of one th e sleep b it o f th e ap pro p riate ch an n e l ( s) is set lo w to activate the c h annel ( s). h o p w i th p i n s y n c the a d 6 6 3 5 i n cl u d e 4 sy nc pi ns t o pr o v i d e t h e m o st accurate sy nc hronization, es pecially between m u ltiple a d 66 35 s. sy nch r on izatio n of ho pp ing t o a n e w n c o fre que ncy wi t h an e x t e r n al si g n al i s acc om pl ishe d wi t h t h e fo llowing m e th o d . 6. unl i k e s o ft sy ncs, pi n sy ncs have ef fect on al l t h e channels at t h e sam e time. see bullet 6 of previous sectio n ?start with soft syn c ? to u n d e rstand th e d e lays b e t w een th e two sets of ch an n e ls. th ese d e lays do n o t occu r w i t h pi n sy nc. 1. not e t h at t h e t i m e from whe n t h e s ync pi n goe s hi g h t o w h e n t h e n c o b e gi ns pr o cessi ng dat a i s t h e cont e n t s of t h e nc o fre q h o l d of f c o u n t e r ( 0 x 8 4 ) + 5 master clock c y cles. hop ho p is a jum p fr om one nco fre q u ency t o a ne w nco fre que ncy . t h i s cha n ge i n f r e que ncy ca n be sy nch r o n i zed vi a m i cropr oce ssor co nt r o l (s oft sy nc) o r a n ext e r n al sy nc si gnal (p in sy nc) as descri be d bel o w. 2. write the nc o fre q hol d of f co unte r(s ) (0 x 8 4 ) t o the appropriate val u e (greater t h a n 1 a n d less than 2^16- 1) . 3. write the nc o fre q uency reg i ster(s) to t h e n e w desi re d fre que ncy . to set t h e nc o f r e que ncy w i t hout sy nc hr o n i zat i on t h e f o llow i ng m e th o d shou ld b e used . 4. set t h e ho p o n pi n sy nc bi t a n d t h e a p pr o p ri at e sy nc pi n e n a b l e hi g h . set fre q no h o p 5. whe n t h e sel e c t ed sy nc pi n i s sam p l e d hi g h by t h e a d 66 35 clk th is en ab les t h e cou n t do wn of th e nc o fre q h o l d of f c o u n t e r . the c o unt er i s cl ocke d with th e ad6 63 5 clk sign al. wh en it reaches a co un t o f on e t h e n e w freq u e n c y is lo ad ed i n to th e nco. 1 . set th e nco freq ho ld off co un ter to 0 . 2. loa d t h e ap pr o p ri at e nc o fre que ncy . t h e n e w freq u e n c y will b e immed i atel y lo ad ed to th e nco. h o p w i th so ft sy n c th e ad663 5 in clud es t h e ab ility to syn c h r on ize a ch an g e in nc o frequ en cy of m u ltip le ch an n e ls or chip s u n d e r m i cropr ocess o r c ont r o l . t h e nc o fre q h o l d of f c o u n t e r (0x8 4) in conju n c tion with t h e ho p b it an d th e sy n c b it (ex t ad dress 4) allow th is synch r on izatio n . basically th e nco freq ho ld off co un ter delays th e n e w frequ e n c y fr om bei ng l o a d ed i n t o t h e n c o by i t s val u e ( num ber of ad 6 6 3 5 c l ks ). the f o l l o wi ng m e t hod i s u s ed t o syn c hron ize a h o p i n freq u e ncy o f m u ltip le ch ann e ls v i a m i cropr ocess o r c ont r o l . 6. unl i k e s o ft sy ncs, pi n sy ncs have ef fect on al l t h e channels at t h e sam e time. see bullet 6 of previous sectio n ?start with soft syn c ? to u n d e rstand th e d e lays b e t w een th e two sets of ch an n e ls. th ese d e lays do n o t occu r w i t h pi n sy nc. parall e l output ports th e ad663 5 in corp orates fou r ind e p e nd en t 16 -b it p a rallel p o rts an d lin k p o rts for o u t p u t d a ta tran sfer. th e p a rallel po rt s a n d l i n k po rt s s h are pi n s an d i n t e rnal m ux ci rcui t r y . for eac h dat a p a t h i . e. f o r e a c h out put p o rt ( a , b , c or d ) ei t h er a pa ral l e l po rt or a l i n k po rt ca n be sel ect ed b u t not bot h. a pa ral l e l po rt a n d a li nk p o rt ca n be use d si m u ltan e o u s ly , bu t o n l y if th ey d o no t sh are th e sam e d a ta p a th ; for ex amp l e parallel port a alon g with link po rt b , o r parallel po rt b with link po rt a. fi g u re 3 6 b e l o w prese n t s a si m p l i f i e d bl oc k di agram sho w i n g t h e 1. note t h at the tim e from whe n the rd y (/dt ack ) pin goe s hi g h t o w h en t h e nc o b e gi ns p r oce ssi n g dat a i s the contents of the nc o fre q h o l d o f f co un t e r (0x 84) + 7 m a ster clock cycles. 2 . write th e nc o freq ho l d off (0 x84 ) cou n t er to th e appropriate val u e (greater t h a n 1 a n d less then 2^16- 1) . 3. write the nc o fre q uency reg i ster(s) to t h e n e w desi re d fre que ncy . 38 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 ad 6 6 3 5 ? s out put dat a ro ut i n g c o n f i g urat i o n f o r o n e out put po rt . link port a c l ock in link port a c l ock out link port a d a t a or 8 lsb ? s of parallel port a dat a (shared p i ns) pclk 0 p a r a ll el por t a m sb da t a pa ra l l e l p o rt a channel indicat o r pa ra l l e l p o rt a i & q i n d i c a to r p o r t a a d 6 6 3 5 8 8 parall el p o rt a re q parall el p o rt a a c k 2 fi gure 3 6 . d a t a r out i n g f o r o u t p ut p o rt a . parallel po rt con f i g uratio n is sp ecified b y accessin g po rt co n t ro l reg i ster ad dr esses 0x1 8 and 0x 1a . por t clo c k master/slav e m o d e (d escrib ed later) is co nfi g ured u s ing t h e p o rt c l oc k c ont r o l regi st e r at a d d r ess 0 x 1 c . it s h o u l d be not e d t h at o u t p ut p o r t s a a n d b have a se parat e cl ock pclk0 fro m o u t pu t ports c an d d (pc l k1 ). no te th at t o access these re gisters, bit 5 (a ccess port c ont rol re gisters) of external a ddress 3 (sle ep register) m u st be set. t h e address is the n selected by pr o g ram m i ng t h e c a r re gi st er at external address 6. th e p a rallel p o rts are en ab led b y settin g b it 7 of th e link co n t ro l r e g i ster s at ad dr esses 0 x19 an d 0x1 b . each p a rallel po rt is cap a b l e of o p e ratin g in eith er ch ann e l m ode or a g c m ode. eac h m ode i s descri be d i n det a i l bel o w. ch annel m o d e parallel po rt c h ann e l m o d e is selected b y set tin g b it 0 of ad dr esses 0x1 8 and 0 x1a . in ch ann e l m o d e , i and q words from ea ch c h annel is directed to the parallel port, b y p a ssi n g th e i n terleav er, in terpo l atin g hal f ban d filter and agc . t h e spe c i f i c cha nnel s out put by t h e p o rt i s sel ect ed b y settin g b its 1 thro ugh 4 o f inpu t po rt c o ntro l reg i ster 0 x18 an d 0x1a . each ch annel 0 thro ugh 3 can b e i nde pen d e n t l y out put o n ei t h e r p o rt a or p o r t b or b o t h . sim ilarly each channel 4 thro ugh 7 ca n be i n depe ndently out put o n ei t h e r p o rt c o r p o r t d or b o t h . channel m ode provides t w o data form ats. each form at req u ires a diffe rent n u m b er o f pa rallel po rt cl ock ( p clk ) cycles to com p lete the transfe r of data. in ea ch case , eac h data elem ent is trans f erre d du ring one pcl k cycle. see fi gu res 3 7 a n d 3 8 , w h i c h p r es ent c h a n nel m ode pa ral l e l po rt t i m i ng. pcl k n t dp re q px r e q pxack t dp p px[ 1 5: 0] i [ 15: 0] q[ 15: 0] pxi q t dp i q p x ch [1 :0 ] p x ch [1 :0 ] = ch a n n e l # t dp ch fi gure 3 7 . c h a nnel m ode i n t e rl eaved f o r m at ( 1 6 - bi t i/ q) . p x [ 1 5: 0] pc l k n t dp re q px r e q px a c k t dp p i [ 15: 8] , q [ 7: 0] px i q t dp i q p x c h [ 1: 0] p x c h [1 :0 ] = c han nel # t dp ch fi gure 3 8 . c h a nnel m ode 8 i / 8 q par al l e l f o r m at . th e 16 -b it in ter l eav ed for m at p r ov id es i and q d a ta fo r each out put sa m p le on bac k -to-ba c k pcl k cycles. both i an d q wo rd s co n s ist of th e full p o rt wi d t h o f 16 b its. data out put i s t r i g ge red o n t h e ri si n g e dge o f pc l k whe n b o t h req a n d ac k are as serted. i data is output during t h e fi rst pc l k cy c l e; and t h e px i q out put i ndi c a t o r pi ns are set h i gh t o ind i cate th at i d a ta is on th e bu s. q d a ta is out put d u ri ng t h e s u bseq ue nt pc lk cy cl e; a n d t h e px i q out put i ndi cat o r pi ns a r e l o w du ri n g t h i s cy cl e. the 8- bi t c o nc ur rent f o rm at pro v i d es 8 bi t s o f i dat a a n d 8 b its of q d a ta si m u ltan e o u s ly d u ring on e pc lk cycle, also t r i gge red o n t h e ri si n g e dge o f pc l k . t h e i by t e occ u pi es th e m o st sig n i fican t b y te o f t h e po rt, wh ile the q b y te occupies t h e le ast signi ficant byte. t h e pxiq (where x = a, b , c or d ) out put i ndi cat o r pi ns a r e set hi gh d u r i n g t h e pclk cycle. no te t h at if d a t a fro m m u ltip l e ch an n e ls are o u t p u t con s ecutiv ely, th e px iq o u t p u t i n d i cato r p i n s will rev. pr b. 7 / 25/2002 39
preliminary technical data AD6635 rem a in h i g h until d a ta fro m al l ch ann e ls h a s b een ou tpu t . it sh ou l d b e n o t ed th at ou tpu t po rts (eith er p a rallel o r link ) a and b ca n out p u t dat a o n l y f r o m channel s 0 t h r o ug h 3 a n d sim i l a rly out pu t po rt s c a n d d can o u t p ut d a t a o n l y fr om chan nel s 4 t h r o ug h 7. pcl k n t dp r e q pxr e q pxac k t dp p px[1 5:0 ] i[1 5:0 ] q[ 15 : 0 ] pxiq t dp iq p x ch [1 :0 ] p x ch[0 ] = a g c # p x ch[ 1] = 0 t dp ch the pac h [ 1 : 0 ] and pb c h [1: 0 ] pi ns pr o v i d e a 2 - bi t bi na ry val u e i n di cat i ng t h e s o urce cha n nel o f t h e dat a cu rren tly b e i ng ou tpu t . th is valu e will co nv ey th e ch ann e l num bers 0 t o 3 . si m i l a rl y pc c h [ 1 : 0 ] a n d p d c h [1: 0 ] pi ns pr o v i d e a 2 - bi t bi na ry val u e i n di cat i ng t h e s o urce cha n nel of t h e dat a c u r r e nt l y bei n g o u t put , t h e c h a n ne l s bei n g 4 t o 7. b i nary val u e ? 0 0 ? i n di cat es chan nel 4 a n d val u e ? 1 1 ? indicates c h annel 7. care sh ou ld b e tak e n to read d a ta fro m th e po rt as so on as p o s sib l e. if n o t, th e sam p le will b e ov erwritt en wh en t h e next ne w dat a sam p l e arri ves. t h i s occ u rs o n a pe r- ch ann e l b a sis; i.e., a ch an nel 0 sam p le will on ly b e o v e rwritten b y a n e w ch ann e l 0 sam p le, etc. fi gure 3 9 . a g c w i t h n o gai n w o r d . pc l k n px r e q px a c k px [ 1 5 : 0 ] t dp re q t dp p i [ 1 5: 0] q[ 1 5 : 0 ] px i q t dp i q ga i n [ 1 5 : 0 ] p x c h [1 :0 ] px ch [ 0 ] = a g c # p x c h [1 ] = 0 p x c h [0 ] = a g c # p x c h [1 ] = 1 t dp ch the or de r of d a t a out put i s de pen d e n t o n w h en dat a ar ri ve d at th e port, wh i c h is is a fun c tio n of t o tal d eci matio n rate, start-ho ldoff valu es, etc. priority o r d e r is, fro m h i g h e st t o l o west , cha n ne l s 0, 1 , 2, 3. ag c m o de parallel po rt c h ann e l m o d e is selected b y clearing b it 0 o f ad dr esses 0x1 8 and 0 x1a . i an d q d a ta ou tpu t in ag c m ode are out p u t f r om t h e a g c , n o t t h e i n di vi d u al channels. paral l el ports a and b can provide data from eith er a g c s a or b or bo th . bits 1 an d 2 of reg i ster add r esses 0 x 1 8 an d 0x 1 a c ont rol t h e i n cl usi o n of dat a fro m agcs a an d b, resp ectiv ely. sim ilarl y p a rallel p o rts c an d d ca n pr ovi de dat a f r o m ei t h er a g c s c o r d or bot h. fig u r e 40 . agc with ga in w o rd . agc m ode p r ovi des o n l y o n e i& q fo rm at , whi c h i s si m ilar to th e 16 -b it in terleav ed form at o f chan n e l m o d e . w h en bo th req an d a c k are a s s e r t ed , th e n e x t r i s i ng edge o f pc lk t r i gge rs t h e out put o f a 1 6 - b i t agc i w o r d for one pcl k cycle. the px i q ( x = a ,b,c or d) out put indicator pins are high during this cycle, a n d is low o t h e rwise. a 16 b it agc q wo rd is prov id ed du ri n g th e subseque nt pc lk cycle. if the ag c g a in wo rd h a s b e en u p d a ted sin c e th e last sam p le, a 16-b it gain word is pr o v i d e d du ri n g t h e pc l k cy cle following t h e q word. master/slave pclk modes th e p a rallel p o rts m a y o p e rat e in eith er master or slav e m ode. t h e m ode i s set vi a t h e po rt c l oc k c ont rol regi st e r (ad d re ss 0x 1c ) . t h e paral l e l po rt s po we r up i n sl a v e m ode t o av oi d pos si bl e c ont e n t i o n s on t h e p c lk pi n. parallel po rts a an d b can be setup in master m o d e wh ile po rt s c a n d d are set u p i n sl a v e m ode or vi c e ve rsa. b u t b o t h th e por ts a an d b o r c an d d shou ld be in sam e m ode si nce t h e y share t h e pa r a l l e l port cl ock pc lk 0 a n d pclk1 respect ively. the dat a pr ovi ded by t h e p a c h [ 1 : 0 ] a n d p b c h [1: 0 ] pi ns i n a g c m ode i s di f f ere n t t h a n t h at p r ovi ded i n c h an nel m o d e . in agc m o d e , pa ch [0 ] and pbch [0 ] ind i cate th e agc so urc e of t h e dat a c u r r e n t l y bei n g out p u t ( 0 = agc a, 1 = agc b). pach[1 ] and pbch[1 ] i n d i cate wh et h e r th e cu rren t d a ta is an d i/ q word or an agc gain wo rd (0 =i/q wo rd , 1=a g c gai n w o r d ) . t h e t w o a g c m ode s are sh own b e low i n fi g u r e s 39 an d 40 . in m a st er m o d e , pc l k i s a n out put w h o s e f r eq ue ncy i s t h e ad 6 6 3 5 cl ock fre que ncy di vi ded by t h e pc lk di vi s o r . si nce val u es f o r pc l k _ d i v i s o r [ 2 : 1 ] ca n ra n g e fr om 0 t o 3, i n t e ger di vi so r s o f 1, 2, 4 o r 8 , res p ect i v el y , can be obt ai ne d. si nc e t h e m a xim u m cl ock rat e o f t h e ad 6 6 3 5 i s 80 m h z, t h e hi ghe st plc k ra t e i n m a st er m ode i s al so 8 0 mhz. master m o d e is selected b y settin g b i t 0 of ad dress 0x 1c . 40 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 in slave m ode, external ci rcu i try p r ov id es the pclk si gnal . sl a v e- m ode pc lk si gnal s m a y be ei t h er syn c hr ono us o r asyn ch ro nou s. th e m a x i m u m slav e- m o d e pclk f r e qu ency is 10 0 mh z. pa ra llel po rt pin functionality th e fo llowing d e scri b e s t h e fu n c tion a lity o f th e p i n s u s ed b y th e p a rallel p o rts. pc lk: i n p u t / out put . as a n out put (m ast e r m ode), t h e max i m u m f r e qu en cy is clk / n , wh er e clk is ad 663 5 cl ock a n d n i s an i n t e ger di vi sor f r om 1, 2, 4 or 8 . as a n in pu t (slav e m o d e ), it m a y b e asyn ch ro nou s relativ e to t h e ad 6 6 3 5 c l k. t h i s pi n po w e rs up as a n i n put t o a voi d pos si bl e c ont e n t i o n s . ot her po rt out put s c h ange o n t h e ri si ng ed ge o f pc lk. req: active hi gh o u tp ut, sy nch r o n o u s to pclk . a lo g i c high o n th is p i n i n d i cates th at d a ta is av ailab l e to b e sh ifted ou t o f th e p o rt. a log i c high v a lu e rem a in s h i g h u n til all p e nd ing d a ta h a s b een sh ifted o u t . ack: active hi gh asy n c h r o n o u s i n p u t. ap ply i ng a l ogi c l o w on t h i s pi n i n hi bi t s pa ral l e l po rt dat a s h i f t i n g. ap pl y i ng a l o g i c hi gh t o t h i s pi n w h e n r e q i s hi g h cau ses t h e p a rallel p o r t t o sh ift o u t d a ta acco r d i ng th e pr o g ram m ed dat a m ode. ac k i s sam p l e d o n t h e ri si n g edge o f pc lk . as sum i ng r e q i s asse rt ed , t h e l a t e ncy fro m th e assert io n of ack t o d a ta app e aring at th e p a rallel po rt out put i s n o m o re t h a n 1. 5 pc l k cy cl es (see fi g u re 1 3 ). ac k m a y b e h e ld h i gh co n tinuo usly; in th is case, whe n dat a bec o m e s avai l a bl e, shi f t i n g be gi n s 1 pc lk cycle after the assertion of r e q (see figure 37). paiq, pbiq, pciq, p d iq: high whe n e v er i data is prese n t on t h e po rt out put , l o w ot he rwi s e. px ch[1 :0 ], pxch [1 :0 ], pcch [1 :0 ], pd ch[ 1 :0 ]: th ese p i n s serv e t o iden tify d a ta i n bo th of th e d a ta m o d e s. in c h an nel m ode, t h ese pi ns f o r m a 2-bi t bi nar y num ber id en tifying th e so urce ch an n e l of th e curren t d a ta word. in agc m ode , [ 0 ] i ndi cat es t h e agc so urc e ( 0 =agc a, 1=a g c b ) , a n d [1] i n di cat es whet her t h e c u rre nt dat a word is (0 =i/q d a ta) or (1 = gain wo rd ). si milarly fo r p a rallel ports c and d [0 ] ind i cates th e agc sou r ce (0= agc c, 1= agc d), and [1] indicates whethe r the cu rren t d a ta wo rd is (0 =i/q data) or (1 = gain word). pa[ 1 5: 0] , pb [ 15: 0] , pc [1 5: 0 ] , pd [1 5: 0] : p a ral l e l out put dat a p o r t s . c o nt ent s a n d f o r m at are m ode- d epe n dent . link port th e ad 663 5 has fo ur con f igur ab le link po r t s th at pro v i d e a seam less d a ta in terface with th e tig e rsharc dsp. each link po rt allo ws t h e ad6 635 to write ou tpu t d a ta t o the recei ve dma channel in the ti gersharc for tra n s f er to m e m o ry. since they op erat e inde pe nde ntl y of each ot he r, eac h l i n k po rt ca n be c o n n ect ed t o a d i ffere nt ti gers h a r c or di f f ere n t l i n k po rt s on t h e s a m e ti gers h a r c . the fi g u r e 41 bel o w s h ows h o w t o c o nnect o n e of t h e fou r ad 663 5 lin k p o r t s to on e of th e fou r ti gers h a r c l i nk p o rt s. in di vi d u al li n k po rt s are co nf igu r ed t h ro ugh th ei r re spective re gisters . AD6635 lcl k i n lclk out lda t pc l k ti gersharc lcl k i n lclk out lda t pc l k 8 fig u r e 41 . link po rt c o n n ect io n between ad 663 5 and tiger s ha rc link por t data f o rm at each l i n k p o rt can out put dat a t o t h e ti ge rs har c i n 5 di ffe re nt f o rm at s: 2 c h an nel , 4 cha nnel , de di c a t e d a g c , red u nda nt ag c wi t h gai n , a n d red u nda nt a g c wi t h o u t gai n . eac h fo r m at out p u t s 2 by t e s o f i dat a and 2 by t e s of q dat a t o f o rm a 4 by t e i q pai r . si nce t h e ti ger s h a r c l i nk po rt t r a n sf ers dat a i n q u a d - w o r d ( 1 6- by t e ) bl oc ks, f o u r iq pai r can m a ke up o n e q u ad -w or d. i f t h e c h an nel dat a i s selected (bit 0 = 0), t h en 4- b y te iq wo rd s of th e fou r ch ann e ls can be ou tpu t in su ccessio n or altern atin g ch ann e l pai r iq w o rds can be out put . the fol l o wi n g fi g u res 4 2 a n d 43 show t h e quad-word tra n s m itted for each scena r io with corres ponding register val u es for c o nfiguri n g each link po rt . ch 3 i,q ( 4 bytes) ch 2 i, q (4 bytes) ch 1 i,q (4 b y tes) ch 0 i , q ( 4 bytes) lin k p o r t a o r b addr 0 x 1 9 or 0x 1 a b i t 0= 0, b i t 1= 0 ch 1 i,q ( 4 bytes) ch 0 i, q (4 bytes) ch 1 i,q (4 b y tes) ch 0 i , q ( 4 bytes) lin k p o rt a ch 3 i,q ( 4 bytes) ch 2 i, q (4 bytes) ch 3 i,q (4 b y tes) ch 2 i , q ( 4 bytes) li nk p o rt b a ddr 0x1 9 and 0x1 a bit 0 = 0 , bit 1 = 1 figure 42. link port data fr om rcf if agc ou t p u t is selected (bit 0 = 1), th en g a in inform ation ca n be se nt with t h e iq pair from each agc. each link po r t can b e co nf igur ed to ou tpu t data f r o m o n e agc o r bot h l i n k p o r t s can o u t put dat a f r om t h e sam e agc. if bo th lin k po rts are tran sm it tin g th e sam e d a ta, th en g a in d a ta m u st b e sen t with th e iq wo rds (bit 2 = 0 ) . no te t h at th e actu al agc g a in is on ly 2 b y tes, so th e lin k rev. pr b. 7 / 25/2002 41
preliminary technical data AD6635 42 rev. pr b. 7 / 25/2002 po rt se nd s 2 by t e s of 0 ? s i m m e di at el y aft e r e ach gai n w o r d to m a k e a fu ll 1 6 -b yte qu ad-w or d. ag c b i q ( 4 bytes) ag c a i , q (4 bytes) ag c b i q (4 b y tes) a g c a i,q ( 4 bytes) li n k p o rt a o r b addr 0 x 1 9 or 0x 1 a b i t 0= 1, b i t 1= 0, b i t 2 = 0 ag c b g a i n ( 4 bytes) ag c b i , q (4 bytes) ag c a g a i n (4 b y tes) a g c a i,q ( 4 bytes) li n k p o rt a o r b addr 0 x 1 9 or 0x 1 a b i t 0= 1, b i t 1= 0, b i t 2 = 1 ag c a g a i n ( 4 bytes) ag c a i , q (4 bytes) ag c a g a i n (4 b y tes) a g c a i,q ( 4 bytes) li nk p o rt a ag c b g a i n ( 4 bytes) ag c b i , q (4 bytes) ag c b g a i n (4 b y tes) a g c b i,q ( 4 bytes) li nk p o rt b addr 0 x 1 9 a n d 0 x 1 a b i t 0= 1, b i t 1= 1, b i t 2=0 fig u r e 43 . link po rt da ta from ag c no te t h at bit 0 =1 bit 1 = 0 , an d bit 2 = 1 is n o t a v a lid co nfigu r ation. bit 2 m u st b e set to 0, to ou t p u t agc a iq and gai n wo r d s o n l i n k po rt a and a g c b iq an d gai n wo rd s on l i n k po rt b . link por t ti ming li nk p o rt s a a n d b r u n of f of pc lk 0 a n d l i n k p o r t s c a n d d run o f f pc lk1, wh ich can b e ex tern ally prov id ed t o th e ch ip (a dd r 0x1c bit 0 = 0 ) or g e n e r a ted fr o m th e m a ster clo c k of th e ad 663 5 (a ddr 0x 1 c bit 0 = 1) . th is r e g i ster bo ot s t o 0 ( s l a v e m ode) a n d al l o ws t h e use r t o c ont rol t h e dat a rat e c o m i ng f r om t h e a d 6 6 3 5 . pc lk can be r u n as f a st as 10 0 mhz. the l i n k p o rt p r o v i d es a 1- by t e dat a wo r d s ( l x[ 7: 0] pi ns ) and o u t p ut cl o c ks (l xc lk o u t pi ns ) i n re s p o n se t o a ready si gnal s ( l xc l k i n pi ns ) from the rece iver, where x = a, b, c or d. each link po rt tran sm its 8 b i ts on each edge o f lc l k out , req u i r i n g 8 lc l k ou t cy cl es t o co m p lete tran smissio n of t h e fu ll 1 6 b y tes o f a ti gers h a r c qua d - w o r d . lclk in tigers h a r c r eady to r e c e ive nex t quad- w o rd tigers h a r c r eady t o rec e i v e quad -w or d lclk ou t w a it > = 6 cy cl e s n e x t q u ad-w or d l d at [ 7 :0] d0 d1 d2 d3 d4 d1 5 d 0 d 1 d 2 fi gure 4 4 . li n k port d a t a tr ansf e r d u e to t h e ti ger s ha rc link po r t p r o t o c o l , th e ad6 635 m u st wait at le ast 6 pclk cy cles after t h e t i gersharc is read y t o receive d a ta, as ind i cated b y t h e ti gersharc set t i ng t h e res p ect i v e a d 6 6 3 5 lc lk in pi n hi g h . o n ce t h e a d 6 6 3 5 l i n k p o r t has wai t ed t h e a p pr o p r i at e num ber of pclk cycles an d h a s b e gun tran sm it tin g d a ta, th e ti gers h a r c doe s a c o nnect i v i t y check by sen d i n g t h e ad66 35 lc lkin low and t h en h i g h wh ile th e d a ta is b e ing tran sm itt ed . th is tells th e ad66 35 link p o rt th at t h e tigersharc?s dm a is ready to recei ve the ne xt qua d - word after co mp letio n of th e c u rrent quad-word. beca use th e conn ectiv ity ch eck is d one in p a rallel to th e d a ta transm ission, t h e AD6635 is ab l e t o st ream uni nt err u pt ed d a ta to t h e ti gersharc. th e len g t h o f th e wait b e fore d a ta tran sm issi o n is a 4 - b it pr o g ram m abl e val u e i n t h e l i n k po rt c ont r o l r e gi st ers (0 x 1 9 an d 0x1 b b its 6 - 3 ) . th is v a l u e allow s t h e a d 66 35 pclk and t h e ti ge rs har c pc lk t o be ru n at di f f e rent rat e s an d ou t o f ph ase. ? ? ? ? ? ? ? ? ? tsharc lclk lclk f f ceil wait _ 34 _ 6 wait en su res th at th e am o unt o f ti m e th e ad663 5 n e ed s to wait to beg i n d a ta tran sm is sio n is at least eq u a l t o the min i m u m a m o u n t of tim e th e tig e rsharc is exp ecting it to wait. if the pclk o f th e ad 663 5 is o u t of p h a se w ith t h e pc l k of t h e ti ger s h a r c an d t h e ar gu m e nt t o t h e ceil() fun c tio n is an i n teg e r, t h en wait m u st b e st rictly great er t h a n t h e val u e gi ve n i n t h e ab o v e fo r m ul a. if t h e lc lks a r e i n pha se, t h en t h e m a xim u m out put dat a rat e i s tsharc lclk lclk f f _ 34 _ 6 15 ? o t h e rwise it is tsharc lclk lclk f f _ 34 _ 6 14 ? tigersh a rc configur ation sin ce th e ad66 3 5 is always t h e tran sm itter i n th is lin k and the tige rsharc is always the receive r, t h e followi ng v a lu es can b e prog ramm ed in to th e lctl reg i ster for th e link port used to receive AD6635 output dat a . ? u ser? means that the actual re gister val u e de pen d s on t h e use r?s ap p lication . v e r e 0 s p d u s e r l t e n 0 psiz e 1 t t o e 0 c e r e 0 l r e n 1 r t o e 1 ta bl e 9 . ti ger s h arc lc t l x regi st er c onf i gur at i o n
preliminary technical data AD6635 AD6635 channel memory map ch addres s regis t e r b i t w i d t h com m e n t s 0 0 -7 f co eff i cien t mem o r y ( c mem) 2 0 1 28x 20- b it mem o r y 8 0 c h a n n e l s leep 1 0: slee p bit from ext_address 3 81 soft _sy n c c o n t rol r e gi st e r 2 1: h o p 0: start 82 pi n_ sy nc c o nt r o l r e gi st er 3 2: fi rst sy n c onl y 1: h o p_ en 0: start _ en 8 3 s t a r t ho l d - o f f co un ter 1 6 s t a r t ho l d - o f f valu e 84 nc o fre q uenc y hol d - o f f c o unt e r 16 nc o _ fr e q h o l d -o ff val u e 85 nc o fre q uenc y r e gi st er 0 16 nc o _ fr e q [ 1 5: 0] 86 nc o fre q uenc y r e gi st er 1 16 nc o _ fr e q [ 3 1: 1 6 ] 87 nc o pha s e of fset r e gi st er 16 nc o _ p h a s e[ 15: 0] 88 nc o c o nt r o l r e gi st er 9 8- 7: sy nc i n put sel ect [1: 0 ] 6 : w b i nput select b/a 5- 4: in p u t e n a b l e c o nt r o l 11: c l oc k on ie n t r ansi t i on t o l o w 10: c l oc k on ie n t r ansi t i on t o hi gh 01: c l oc k on ie n hi g h 00: mas k on ie n l o w 3: clear pha s e acc u m u lator on hop 2: am pl i t ude di t h e r 1: p h ase dit h er 0: by-pa ss ( a - i nput -> i - p a th, b -> q) 89 - 8 f u n use d ta bl e 1 0 . c h a nnel ad dress mem ory m a p 0x 0 0 - 0 x7f : c o ef ficient me mor y ( c me m ) this is t h e coe fficient m e m o r y (c-m em ) use d by the rcf. it is m e m o ry m a pped as 128 w o rds by 20 bits. a second 128 words of r a m may be accesse d via this sam e l o cat i on by wri t i ng bi t 8 o f t h e r c f co nt r o l regi st er hi gh at ch ann e l ad dress 0x a4 . th e fi lter calcu lated will always use t h e sam e coefficients for i a n d q. by us ing m e m o ry fro m b o t h of these 128 b l o c k s a filter up t o 16 0 tap s can b e calcu lated . mu ltip le filters can b e lo ad ed an d selected with a single internal access to the c o efficient offset r e gi st er at c h a nnel a d dres s 0 x a 3 . 0x80: channel sleep re gis t er thi s regi st er c ont ai n s t h e sl eep bi t f o r t h e c h a nnel . wh en t h is b it is h i g h th en th e ch ann e l is p l aced in a low p o wer state. wh en t h is b it is lo w th en t h e ch ann e l pr ocesses dat a . t h i s bi t ca n a l so be set by ac cessi ng t h e sleep re gister at e x ternal ad dress 3. whe n the e x ternal sleep re gister is accesse d t h en all four c h a nnels are accessed sim u ltaneously and t h e sleep bits of the channels a r e se t appropriately. 0 x81 : so ft_ sy nc r e g i st er th is reg i ster is u s ed t o in itiate sync ev en ts th ro ugh th e micro po rt. if t h e hop b it is written h i g h th en th e hop h o l d -o ff c o unter at add r ess 0x 84 is lo ad ed an d b e g i ns to co un t d o wn . wh en t h is v a lue reach e s 1 then th e nc o fre que ncy re gi st er u s ed by t h e nc o acc um ul at or , i s lo ad ed with t h e d a ta fro m channel a d dres se s 0x85 and 0 x86 . wh en t h e start b it is set h i gh th en the start ho l d - off coun ter is lo ad ed with t h e v a lu e at ad dress 0x8 3 and b e g i n s t o co un t do wn . wh en t h is v a lu e h its 1 th en th e sleep b it in add r ess 0x8 0 is dropp ed low and th e ch ann e l i s started. 0 x82 : p i n_ syn c r e g i s t er th is reg i ster is u s ed t o co n t rol th e fun c tio n a l ity o f th e sy nc pi ns. a n y o f t h e f o ur sy nc pi ns ca n be c h o s en and m oni t o re d by t h e c h a nnel . t h e c h an nel c a n be co nfigu r ed t o i n itiate eith er a start or hop sync ev en t b y settin g th e hop or start b it h i gh . th ese b its fu n c tion as en ab les so th at wh en a sync p u l se o c cu rs then eith er th e start or hop ho ld-off cou n t ers are activ ated in th e sam e m a nner as wi t h a s o ft _s ync . 0 x83 : st a r t ho ld-off c o unter th e start ho ld-off c o u n t er is lo ad ed with t h e v a lu e written t o th is ad dress wh en a start_syn c is in itiated . it can b e in itiated b y eith er a soft_ s ync o r pin_ sync. the c o unter be gins dec r em enting a n d whe n i t reaches a val u e o f 1 t h e chan nel i s br o u ght o u t o f sle e p a n d be gi ns pr ocessi ng dat a . if t h e c h an n e l i s al ready ru nni ng t h e n t h e p h a se o f t h e filters are adju sted su ch th at m u ltip le a d 66 35 s can b e sy n c hr on ized . a p e r i od ic p u l se on t h e rev. pr b. 7 / 25/2002 43
preliminary technical data AD6635 sy nc pi n ca n be use d i n t h i s way t o a d ju st t h e t i m i ng of th e filters with th e reso lu ti o n o f th e adc sam p le clo c k . if th is reg i ster is written t o a 1 t h en th e start will o ccu r immediately when the sync com e s in to th e ch ann e l. if it is written t o a 0 th en no sync will o c cu r. b i t s 8- 7 of t h i s re gi st er c h o o s e w h i c h o f t h e fo ur s ync pins are use d by the cha n nel. the sync pin selected ca n b e u s ed to in itiate a start, hop, o r timin g ad ju stm e n t to t h e c h a n nel . the sy nc hr oni zat i on sect i o n of t h e dat a - sh eet p r ov id es m o re d e tails on th is. 0x84: nco f requenc y h o l d -o ff coun ter bit 6 of th is reg i ster d e fi n e s t h e inpu t used by th e ch ann e l. for c h an nel s 0 t h r o u g h 3, t h e i n p u t po rt ca n b e a o r b , wh ile for ch ann e ls 4 throug h 7 , t h e inpu t port can b e c o r d. for ch an n e l s 0 t o 3 , if th is b it is low th en in pu t port a is selected and i f th is b it is h i gh in pu t port b is selected . fo r ch ann e ls 4 t o 7, if t h is b it is l o w th en i n pu t po rt c is selected and i f th is b it is h i gh in pu t port d is selected . each ch ann e l can sel ect its in pu t port ind i v i du ally. each inp u t p o rt co n s ists of a 14-b it inpu t man tissa(inx[1 3 : 0 ] ), a 3-b it exponent ( expx[2 :0 ]) and a in pu t en ab le p i n ienx . th e x represen ts either a, b, c o r d. th e nco frequ e n c y ho ld-off coun ter is l o ad ed with th e v a lu e written to th is add r ess wh en eith er a so ft _ s ync or pi n_ sy nc c o m e s i n t o t h e ch annel . t h e c o unt e r begi ns cou n t i n g do w n so t h at whe n i t reac hes 1 t h e nc o fre que ncy wo r d i s u pdat e d wi t h t h e val u es of ad dres ses 0 x85 an d 0x8 6. th is is kn own as a h o p o r h op_ sy n c . if th is reg i ster is written t o a 1 t h en th e nc o frequ e n c y will b e u p d a ted immed i ately wh en th e sync comes in to th e ch ann e l. if it i s written to a 0 th en no hop will o ccur. nc o h o ps ca n be ei t h e r pha se co nt i n uo us or n o n - pha se cont i n u o u s dep e ndi ng u p o n t h e st at e of bi t 3 of t h e nc o co n t ro l reg i ster at ch an n e l address 0 x88 . when th is b it is low t h en the phase acc u m u la to r of the nc o is not cleare d but st art s t o ad d t h e ne w nc o f r eq ue ncy wo rd t o t h e accum u lator as soon as t h e sync occ u rs. if this bit is high the n t h e phase acc u m u la tor of the nc o is cleared to 0 an d th e n e w word is th en accu m u lated . bits 5 - 4 d e termin e h o w t h e sa m p le clo c k for th e ch ann e l is deri ved f r om t h e hi g h s p ee d c l k si gnal . t h ere are f o u r pos si bl e c hoi ce s. eac h i s de fi ned bel o w b u t fo r fu rt he r d e tail th e n c o sectio n of the d a ta sh eet should b e co nsu lted. wh en t h ese b its are 00 th en t h e in pu t sam p le rate (f sam p ) of th e ch ann e l is eq u a l t o the rat e of th e h i g h sp eed clk sig n a l. wh en ien is l o w th e d a ta go ing i n to th e ch ann e l is m a sked t o 0. thi s i s a n a p pr op ri at e m ode f o r td d syste m s where the recei ver ma y wish to m a sk off the tran sm it ted d a t a yet still re m a in in t h e p r op er ph ase for t h e next receive burst. 0x 8 5 : n c o f requenc y regi ster 0 thi s regi st er re prese n t s t h e 16 lsb s of t h e n c o fre que ncy word. t h ese bits a r e s h adowed a n d are not u p d a ted to t h e reg i ster u s ed fo r th e p r o cessi n g un til th e ch ann e l is either b r o ugh t ou t o f sleep o r a so ft _ s ync or pin _ sync h a s b e en issu ed. in th e latter two cases th e regi st er i s u p d a t ed w h e n t h e f r eq ue ncy h o l d -o ff c o unt e r h its a v a lu e of 1 . if th e fr equen c y ho ld-off co un ter is set to 1 th en the reg i ster will b e up d a ted as soon as th e sh ad ow is written . wh en t h ese b its are 01 th en t h e in pu t sam p le rate is det e rm i n ed by t h e f r act i o n of t h e ri si n g e d ge s o f c l k on wh ich th e ien in pu t is h i gh . fo r ex am p l e if ien togg les o n ev ery risi n g edg e o f clk th en th e ien si g n a l will on ly be sam p l e d hi g h on 1 o u t of e v ery 2 ri si n g e dge s of c l k. th is m ean s th at th e inp u t samp le rate f sam p will b e ? th e clk rate. 0x 8 6 : n c o f requenc y regi ster 1 this register re prese n ts t h e 16 msbs of t h e nco fre que ncy word. t h ese bits a r e s h adowed a n d are not u p d a ted to t h e reg i ster u s ed fo r th e p r o cessi n g un til th e ch ann e l is either b r o ugh t ou t o f sleep o r a so ft _ s ync or pin _ sync h a s b e en issu ed. in th e latter two cases th e r e g i ster is upd ated on ly wh e n the freque ncy hol d -off c o u n t e r hi t s a val u e o f 1. if t h e f r e que ncy hol d - o f f co un ter is set to 1 th en t h e reg i ster will b e up d a ted as soon as th e sh ad ow i s written . wh en t h ese b its are 10 th en t h e in pu t sam p le rate is d e term in ed b y th e rate at wh ich th e ien p i n to gg les. th e dat a t h at i s ca p t ure d on t h e ri s i ng e d ge of c l k a f t e r ien tran sitio ns from lo w to h i g h is pro c essed. wh en t h ese b its are 11 the n the accum u lator a n d sam p le clk a r e d e term in ed b y th e rate at wh ich th e ien p i n to gg les. th e dat a t h at i s ca p t ure d on t h e ri s i ng e d ge of c l k a f t e r ien tran sitio ns from h i g h to l o w is pro c essed. fo r ex am p l e, cont rol m odes 10 an d 1 1 ca n be use d t o al l o w i n t e rl eave d dat a f r om ei t h er t h e a o r b i n put p o rt s a n d t h en assi g n e d to th e resp ective ch an n e l. th e ien p i n selects th e d a ta suc h t h at a cha nnel c o ul d be c o n f i g ure d i n m ode 1 0 a n d anot her co ul d be c o n f i g ure d i n m ode 11 . 0 x87 : nco pha s e off s et reg i st er th is reg i ster rep r esen ts a 16 -bit p h a se offset t o th e nc o. it can be i n t e r p ret e d as val u es ran g i n g fr om 0 t o ju st u n d er 2 44 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 accum u lator is cleared t o 0 be fore it be gins a ccum u lating the ne w fre que n cy word. t h i s is appropriate when m u lt i p l e chan n e l s are ho p p i n g fr om di ffe rent fre que nci e s t o a c o m m on fr eque ncy . bits 2 - 1 co n t rol wh et h e r or n o t th e d ithers of th e nc o are activ ated . th e u s e of th ese featu r es is h e av ily d e term in ed b y th e syste m co nstrain t s. c o n s u lt th e nc o section o f the d a ta sh eet fo r m o re d e tailed in fo rm atio n on th e use o f d ith er. bit 0 of th is reg i ster allows t h e nco frequ e n c y tran slatio n st age t o be by p a ssed. whe n t h i s occu rs t h e dat a f r om t h e a i n put p o rt i s passe d d o w n t h e i pat h of t h e cha nnel a n d th e d a ta fro m th e b inpu t po rt is p a ssed down th e q p a t h o f th e ch an n e l. th is allo ws a real filter to b e p e rfo r m e d on base ban d i a n d q dat a . ad 6 6 3 5 ch a nnel me m o r y ma p ( c ontin u ed ) ch addres s regis t e r b i t w i d t h com m e n t s 90 rc ic 2 deci m a ti on ? 1 12 m rcic2 -1 91 rc ic 2 i n t e r pol at i on ? 1 9 l rcic2 -1 92 rc ic 2 scal e 12 11: ex p one nt i nve rt 10: ex p one nt w e i g ht 9- 5: rc ic 2_ q u ie t[ 4: 0] 4- 0: rc ic 2_l ou d[ 4: 0] 9 3 reserv ed 8 reserv ed (m u s t b e written low) 9 4 c i c 5 deci m a tion ? 1 8 m cic5 -1 95 c i c 5 s cal e 5 4- 0: c i c 5 _sc a le [4: 0 ] 9 6 reserv ed 8 reserv ed (m u s t b e written low) 97 - 9 f u n use d a0 r c f deci m a t i on ? 1 8 m rcf -1 a1 rcf decim a tion phase 8 p r c f a2 r c f n u m b er of tap s ?1 8 n taps -1 a3 rcf coefficient offs et 8 co rcf a4 rcf con t ro l r e g i ster 1 1 1 0 : rcf by-pass bist 9: r c f in p u t sel ect ( o w n 0, ot he r 1) 8: p r o g ram r a m b a n k 1/ 0 7: us e c o m m on ex po ne nt 6: f o rce o u t put scal e 5- 4: out put fo rm at 1x : flo a ting po in t 12 +4 01 : flo a ting po in t 8 + 4 00 : fix e d po in t 3- 0: out put sc al e a5 bist si gnature for i path 1 6 b i st- i a6 bist si gnature for q path 1 6 b i st- q a7 # of bist outputs to accum u late 20 19-0: # of out puts(c ounter va lue read) a8 ram bist con t ro l reg i ster 3 2 : d-ram fail/pass 1 : c - ram fail/pass 0: r a m bi s t ena b le a9 out put c o nt rol r e gi st er 9: map rcf data to b i st r e gisters 5: o u t p ut f o rm at 1 : 1 6 -b it i an d 16-b it q 0 : 1 2 -b it i an d 12-b it q ta bl e 1 1 . c h a nnel ad dress mem ory m a p 0x 9 0 : r c ic 2 deci ma ti on ? 1 (m rcic2 -1 ) th is reg i ster is u s ed t o set th e d ecim a tio n in th e rc ic2 filter. th e v a l u e written t o this reg i ster is the d ecim a tio n m i nus one . t h e rc ic 2 deci m a t i on ca n ran g e fr om 1 t o 40 9 6 depe n d i n g up o n t h e i n t e rp ol at i o n o f t h e cha nnel . the decim a tion m u st always be greater tha n the in terpo l atio n. m rcic2 m u st be chosen large r t h an l rcic2 and bot h m u st be c hos en suc h t h a t a sui t a bl e rc i c 2 scal ar can b e ch osen. for m o re d e tails th e rcic2 sectio n shou ld b e co nsu lted 0x 9 1 : r c ic 2 interp ol a t i o n ? 1 (l rcic2 -1) rev. pr b. 7 / 25/2002 45
preliminary technical data AD6635 th is reg i ster is u s ed t o set th e in terp o l ation i n th e rc ic2 filter. th e v a l u e written t o this reg i ster is the in terp o l ation m i nus one . t h e rc ic 2 i n t e rp ol at i on c a n ra n g e fr om 1 t o 51 2 de pen d i n g u p o n t h e deci m a t i on o f t h e r c ic 2. t h ere i s no tim i ng error associated wit h th is in terp o l atio n . see t h e rcic2 sectio n of the data s h e e t fo r fu rthe r d e tails. 0x 9 2 : r c ic 2 scal e the rc ic 2 sca l e regi st er i s us ed t o p r ovi de a t t e nuat i o n t o co m p en sate fo r th e g a in of th e rcic 2 an d to ad ju st t h e lin earizatio n of th e d a ta fro m th e flo a ting - po in t inp u t . th e use of t h i s scal e re gi st er i s i n f l uence d bot h b y t h e rc ic 2 g r o w t h and fl oatin g po in t in pu t po rt c o nsideratio n s . th e rc ic 2 sect i o n sho u l d be c ons ul t e d fo r det a i l s . t h e rc ic 2 scalar ha s been com b ined wi th t h e ex p o n e n t o f f s e t an d will n eed to b e h a n d l ed ap prop riately in b o t h th e inpu t po rt and rc ic 2 sect i ons . b i t 11 det e rm ines t h e pol ari t y of t h e e x po n e nt . n o rm al l y , th is b it will b e cleared un less an d adc su ch as th e ad66 00 is u s ed , i n wh ich case th is b it will be set. b i t 10 det e rm ines t h e wei g ht of t h e e x po ne n t wo r d asso ciated with th e inpu t port. wh en th is b it is lo w th en each e x ponent step is c o nside r ed to be worth 6.02db . wh en t h is b it is h i g h th en each ex pon en t step is con s id ered t o be w o rt h 1 2 . 0 2 d b . bits 9-5 are the actual scale va lue used whe n the le vel indicator, l i pi n ass o ciated wi th this c h a nnel is active. bits 4-0 are the actual scale va lue used whe n the le vel indicator, l i pi n ass o ciated wi th this c h a nnel is active. 0 x93 : reserv ed (m u s t b e written low) 0 x94 : cic5 decima t i on ? 1 ( m cic5 -1 ) th is reg i ster is u s ed t o set th e d ecim a tio n in th e cic 5 filter. th e v a l u e written t o this reg i ster is the d ecim a tio n m i nus one . al t h o u g h t h i s i s a n 8- bi t re gi st er t h e deci m a ti on i s u s ual l y l i m i t e d t o bet w ee n 1 a n d 32 . deci m a t i ons hi ghe r t h an 3 2 w oul d req u i r e m o re scal i n g than t h e cic 5 i s capa b le of. 0 x95 : cic5 sca l e the c i c5 scale factor is us ed to co mp e n s a te fo r th e g r o w t h o f th e cic5 filter. c o n s u lt th e cic 5 section for d e tails. 0 x96 : reserv ed (mu s t b e written l o w) 0x a 0 : r c f d eci mati o n ? 1 (m rcf -1 ) th is reg i ster is u s ed t o set th e d ecim a tio n o f th e rcf stag e. th e v a l u e written is t h e d ecim a tio n min u s o n e . alth oug h th is i s an 8-b it reg i ster wh ich allows d ecim a t i o n u p to 25 6, for m o st filterin g scen ari o s th e deci m a tio n sho u l d be l i m i t ed bet w ee n 1 a n d 3 2 . hi g h er deci m a ti ons are allowed but th e alias pro t ectio n o f th e rc f m a y n o t b e acceptable for som e applications . 0xa1: rcf decimation p h ase (p rcf ) th is reg i ster allo ws an y on e of th e m rcf pha ses of t h e filter to b e u s ed an d can b e ad ju sted d y n a m i cally. each ti m e a filter is started th en t h i s ph ase is upd ated . when a ch ann e l is sy n c h r on ized t h en it will retain th e ph ase setting cho s en he re. t h i s ca n be used as part of a t i m i ng rec o very lo op with an ex tern al pro c esso r or can allow m u lt ip le rcfs to work t o g e t h er wh ile u s ing a sing le rcf p a ir. th e rcf sectio n of th e d a ta sh eet sh ou l d b e co n s u lted for fu rthe r details. 0xa2: rcf number of taps minus one (n rcf -1 ) th e nu m b er of tap s for t h e r c f filter m i n u s on e is written here . 0x a 3 : r c f c o ef ficient of fs et ( c o rcf ) th is reg i ster is u s ed t o sp ecify wh ich section o f th e 25 6- word co efficien t m e m o ry is u s ed for a filter. it can b e u s ed to select b e t w een m u ltip le filt ers th at are l o ad ed in to m e m o ry and re fere nced by t h i s p o inter . this re gister is sh ad owed an d th e filter po in t e r is u p d a ted ev ery tim e a n e w filter is started . th is allows the co effici en t offset to b e written ev en wh ile a filter is b e ing co m p uted with di st ur bi n g o p er at i on. t h e nex t sam p l e t h at com e s out of th e rcf will be with t h e n e w filter. 0 x a4 : rc f co ntro l r e g i st er th e rcf con t ro l reg i ster is an 11-bit regist er that cont rol s ge nera l feat ure s of t h e r c f as wel l as o u t p ut fo rm att i ng. th e bi t s of t h i s re gi st er a n d t h ei r f unct i o ns a r e descri bed bel o w. bit 1 0 b y p a sses th e rcf filter an d send s th e cic5 ou tpu t dat a t o t h e b i s t -i an d b i st - q r e gi st ers . t h e 16 m s b s of the cic 5 data can be access e d from this register if bit 9 of t h e r c f c ont r o l r e gi st er 2 at cha nnel a d dre ss 0 x a 9 i s set . bit 9 of th is reg i ster co n t ro ls th e so urce o f th e inpu t d a ta to th e rcf. if th i s b it is 0 th en t h e rcf pro cesses th e ou tpu t d a ta of it?s own ch ann e l. if t h is b it is 1 t h en it p r o cesses t h e dat a fr om t h e c i c 5 of an o t her c h a nnel . the c i c 5 t h at th e rcf is conn ected t o wh en th is b it is 1 are sho w n i n t h e tab l e 12 b e low. th ese can b e u s ed to allo w m u l tip le rcfs t o be u s ed t o ge t h er t o pr ocess wi de r ban d w i d t h cha n nel s . see th e m u lti-processing sect io n of th e d a ta-sh eet for fu rthe r details. ch ann e l rcf inpu t source wh en bit-9 is 1 0 1 1 0 2 1 3 1 4 5 5 4 46 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 rev. pr b. 7 / 25/2002 47 6 5 7 5 table 12. rcf input configurations bit 8 is used as an extra address to allow a second block of 128 words of cmem to be addressed by the channel addresses at 0x00-0x7f. if this bit is 0 then the first 128 words are written and if this bit is 1 then a second 128 words is written. this bit is only used to program the coefficient memory. it is not used in any way by the processing and filters longer than 128 taps can be performed. bit 7 is used to help control the output formatting of the AD6635s rcf data. this bit is only used when the 8+4 or 12+4 floating-point modes are chosen. these modes are enable by bits 5 and 4 of this register below. when this bit is 0 then the i and q output exponents are determined separately based on their individual magnitudes. when this bit is 1 then the i and q data is a complex floating- point number where i and q use a single exponent that is determined based on the maximum magnitude of i or q. bit 6 is used to force the output scale factor in bits 3-0 of this register to be used to scale the data even when one of the floating point output modes is used. if the number was too large to represent wi th the output scale chosen then the mantissas of the i and q data clip and do not overflow. bits 5 and 4 choose the output formatting option used by the rcf data. the options are defined in the table 13 below and are discussed further in the output format section of the data sheet. bit values output option 1x 12-bit mantissa and 4-bit exponent(12+4) 01 8-bit mantissa and 4-bit exponent(8+4) 00 fixed point mode table 13. output formats bits 3-0 of this register repr esent the output scale factor of the rcf. it is used to scale the data when the output format is in fixed-point mode or when the force exponent bit is high. 0xa5: bist register for i this register serves two purposes. the first is to allow the complete functionality of the i data path in the channel to be tested in the system. the bist section of the data sheet should be consulted for further details. the second function is to provide access to the i output data through the micro-port. to accomplish this the map rcf data to bist bit in the rcf control register 2, 0xa9, should be set high. 16-bits of i data can then be read through the micro port in either the 8+4, 12+4, 12 bit linear or 16-bit linear output modes. this data may come from either the formatted rcf output or the cic5 output. 0xa6: bist register for q this register serves two purposes. the first is to allow the complete functionality of q data path in the channel to be tested in the system. the bist section of the data sheet should be consulted for further details. the second function is to provide access to the q output data through the micro-port. to accomplish this the map rcf data to bist bit in the rcf control register 2, 0xa9, should be set high. 16-bits of q data can then be read through the micro port in either the 8+4, 12+4, 12 bit linear or 16-bit linear output modes. this data may come from either the formatted rcf output or the cic5 output. 0xa7: bist control register this register controls the number of outputs of the rcf or cic filter that are observed when a bist test is performed. the bist signature registers at addresses 0xa5 and 0xa6 will observe this number of outputs and then terminate. the loading of this register also starts the bist engine running. details of how to utilize the bist circuitry are defined in the bist section of the data sheet. 0xa8: ram bist control register this register is used to test the memories of the AD6635 should they ever be suspected of a failure. bit 0 of this register is written with a 1 when the channel is in sleep and the user waits for 1600 clks and then polls the bits. if bit 1 is high then the cmem failed the test and if bit 2 is high then the data memory used by the rcf failed the test. 0xa9: output control register bit 9 of this register allows the rcf or cic5 data to be mapped to the bist registers at addresses 0xa5 and 0xa6. when this bit is 0 then the bist register is in signature mode and ready for a self-test to be run. when this bit is 1 then the output data from the rcf after formatting or the cic5 data is mapped to these registers and can be read through the micro-port. bits 5 determines the word length used by the parallel port. if this bit is 0 then the parallel port uses 12 bit words for i and q. if this bit is 1 then the parallel port uses 16 bit words for i and q. when the fixed point output option is chosen from the rcf control re gister then these bits also set the rounding correctly in the output formatter of the rcf. remaining bits in this register are reserved and should be written low when programming.
preliminary technical data AD6635 memory map for input port control registers ch add ress register bit wid t h co m m e n t s 00 l o wer t h r e shold a 10 9- 0: l o wer t h r e shold f o r i nput a 01 upper t h r e shold a 10 9- 0: upper t h r e s hold f o r i nput a 02 dwell t i m e a 20 19- 0: m i nim u m tim e below l o wer t h r e shold a 03 gain range a contr o l register 5 4: output polarity lia - a & lia - b 3 : in te rleav ed ch an n e ls 2- 0: l i near izatio n hold- o ff regist er 04 l o wer t h r e shold b 10 9- 0: l o wer t h r e shold f o r i nput b 05 upper t h r e shold b 10 9- 0: upper t h r e s hold f o r i nput b 06 dwell t i m e b 20 19- 0: m i nim u m tim e below l o wer t h r e shold b 07 gain range b contr o l register 5 4: ou tp u t po la rity lib-a & lib-b 3 : in te rleav ed ch an n e ls 2- 0: l i near izatio n hold- o ff regist er ta bl e 1 8 . i n put port c o nt rol regi st ers th is word is 10 b its wi d e an d m a p s to th e 10 m o st si gni fi ca nt bi t s o f t h e m a nt i s sa. if t h e up pe r 10 bi t s of in pu t port a are greater t h an o r equ a l to th is v a lu e, th en t h e up pe r t h res hol d has bee n m e t. in n o rm al chi p ope rat i o n, th is will cau se th e approp riate li p i n (lia-a or lia-b) t o becom e active. in orde r t o acc ess the input port re gisters t h e ?access inpu t / ou tpu t co n t ro l reg i sters? b it (b it 5) o f sleep register (a dd re ss 0 x 3 ) sh o u ld be set. the ca r (cha n n el add r ess reg i st er, ex tern al add r ess 0x6 ) is then written with the address t o t h e c o rrect input port register. for c h an nel s 0 t o 3 an d i n p u t po rt s a a n d b chi p sel ect 0 (/ c s 0 ) s h o u l d be use d whi l e pr o g ram m i ng usi n g micro p o r t. similarly fo r ch ann e ls 4 to 7 and in pu t ports c and d chi p sel ect 1 (/ c s 1 ) s h oul d be use d w h i l e pr o g ram m i ng usi n g m i crop or t . 0x02 dwell time a: th is sets t h e ti me th at th e inpu t sign al m u st b e at o r b e l o w th e lower th resh o l d b e fo re th e li p i n is d e -activ ated . for th e inp u t lev e l d e tecto r to wo rk , t h e dwell ti me m u st b e set to at least 1. if set to 0 , th e li fu n c tion s are d i sab l ed . no te: for th e reg i sters i n th e ab ov e tab l e, i n p u t po rts a an d b sh ou ld be du p licated w i th inp u t po r t s c and d wh en chi p sel ect 1 (/ c s 1) i s us ed instead of (/cs0) while pr o g ram m i ng t h e m i crop ort . sim i l a rl y channel s 0 t o 3 shoul d also be duplicated w i t h c h an nel s 4 t o 7 w h ere v er m e nt i oned . th is is a 20 b it reg i ster. wh en th e lower th resho l d is m e t fol l o wi n g a n e x cu rsi o n i n t o t h e up pe r t h res hol d, t h e dwel l t i m e count er i s l o ade d a n d be gi ns t o c o unt h i gh spee d clo c k cycles as lo ng as th e inpu t is at o r b e l o w th e lower t h res hol d. i f t h e si gnal i n cre a ses ab o v e t h e l o we r th resh o l d , t h e co un ter is rel o ad ed and waits fo r th e si g n a l to fall b e low the lo wer t h resho l d ag ain. inpu t p o rt contr o l re gister s the in p u t p o rt cont rol regi st e r ena b l e s vari o u s i n put related featu r es u s ed p r im arily fo r i n pu t d e tectio n an d lev e l cont rol . depe ndi ng o n t h e m ode o f o p erat i o n, u p t o 4 di ffe re nt si g n al pat h s ca n be m oni t o red wi t h t h ese registers . thes e features a r e a ccessed by sett ing bit 5 of ext e r n al ad d r es s 3 (sl e e p r e gi st er) a n d t h e n usi n g t h e car (e xternal address 6) to a d dress t h e 8 l o cations available. 0 x03 ga in rang e a co nt ro l r e g i st er: bit 4 d e term in es th e po larity o f lia-a and lia-b. if th is b it is clear t h en th e li si g n a l i s h i g h wh en the up p e r t h res hol d has b een e x cee ded . ho wev e r, if t h is b it is set, th e li p i n is l o w wh en activ e. th is allo ws max i m u m flex ib ility wh en u s ing t h is fun c tio n. bit 3 d e term in es if th e inp u t co nsists of a sin g l e ch an n e l or tdm ch ann e ls su ch as wh en u s ing t h e ad66 00 . if t h is b it is cleared , th en a sing le adc is assu m e d . in th is m o d e , lia-a functions as the acti v e o u t p ut i n di cat or . l i a-b p r ov id es t h e com p l i m en t o f lia-a. howev e r, if th is b it is set, th en th e inp u t is d e term in ed to b e du al ch ann e l an d determ ined by the state of t h e ien a pin . if the ien a pin is lo w, th en t h e in pu t d e tection is d i rected to lia-a. if t h e iena p i n is h i g h , th e inp u t is d i rected to lia-b. in eith er case, b it 4 d e term in es th e actual p o l arity o f th ese si g n a ls. resp on se to t h ese settin g s is d i rected to t h e lia-a, l i a-b, lib-a an d lib-b p i n s . 0x00 l o wer threshol d a: th is word is 10 b its wi d e an d m a p s to th e 10 m o st si gni fi ca nt bi t s o f t h e m a nt i s sa. if t h e up pe r 10 bi t s of in pu t port a are less th an o r eq u a l t o th is v a l u e, t h en th e l o we r t h res hol d has bee n m e t. in n o rm al chi p ope rat i o n, t h i s st art s t h e dwel l t i m e count e r . i f t h e i n put si g n al in cr eases above th is v a lu e, then th e coun ter is r e lo ad ed and awaits th e i n put to dro p b a ck t o th is lev e l. bit 2 - 0 d e term i n es t h e in tern al laten c y of th e g a in d e tect fu nct i o n. whe n t h e li a - a , b pi ns are m a de act i v e, t h ey 0x01 upper th reshold a: 48 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 are typically us ed to cha n ge a n attenuator or gain stage. sin ce th is is prio r t o th e adc , th ere is a laten c y asso ciated with th e adc an d with th e settlin g of th e g a i n ch ang e . th is reg i ster allo ws t h e i n ternal d e lay of th e lia-a,b si gnal t o be pr og ram m ed. 0x04 l o wer threshol d b: th is word is 10 b its wi d e an d m a p s to th e 10 m o st si gni fi ca nt bi t s o f t h e m a nt i s sa. if t h e up pe r 10 bi t s of in pu t port b are less th an o r eq u a l t o th is v a l u e, t h en th e l o we r t h res hol d has bee n m e t. in n o rm al chi p ope rat i o n, t h i s st art s t h e dwel l t i m e count e r . i f t h e i n put si g n al in cr eases above th is v a lu e, then th e coun ter is r e lo ad ed and awaits th e i n put to dro p b a ck t o th is lev e l. 0x05 upper th reshold b: th is word is 10 b its wi d e an d m a p s to th e 10 m o st si gni fi ca nt bi t s o f t h e m a nt i s sa. if t h e up pe r 10 bi t s of in pu t port b are greater t h an o r equ a l to th is v a lu e, th en t h e up pe r t h res hol d has bee n m e t. in n o rm al chi p ope rat i o n, th is will cau se th e approp riate li p i n (lib-a or lib-b) to becom e active. 0x06 dwell time b: th is sets t h e ti me th at th e inpu t sign al m u st b e at o r b e l o w th e lower th resh o l d b e fo re th e li p i n is d e -activ ated . for th e inp u t lev e l d e tecto r to wo rk , t h e dwell ti me m u st b e set to at least 1. if set to 0 , th e li fu n c tion s are d i sab l ed . th is is a 20 b it reg i ster. wh en th e lower th resho l d is m e t fol l o wi n g a n e x cu rsi o n i n t o t h e up pe r t h res hol d, t h e dwel l t i m e count er i s l o ade d a n d be gi ns t o c o unt h i gh spee d clo c k cycles as lo ng as th e inpu t is at o r b e l o w th e lower t h res hol d. i f t h e si gnal i n cre a ses ab o v e t h e l o we r th resh o l d , t h e co un ter is rel o ad ed and waits fo r th e si g n a l to fall b e low the lo wer t h resho l d ag ain. 0 x07 ga in rang e b control re gister : bit 4 d e term in es th e po larity o f lib - a and lib-b. if t h is b it is clear t h en th e li si g n a l i s h i g h wh en the up p e r t h res hol d has b een e x cee ded . ho wev e r, if t h is b it is set, th e li p i n is l o w wh en activ e. th is allo ws max i m u m flex ib ility wh en u s ing t h is fun c tio n. bit 3 d e term in es if th e inp u t co nsists of a sin g l e ch an n e l or tdm ch ann e ls su ch as wh en u s ing t h e ad66 00 . if t h is b it is cleared , th en a sing le adc is assu m e d . in th is m o d e , lib-a functions as the acti v e o u t p ut i n di cat or . l i b - b p r ov id es t h e com p l i m en t o f lib-a. howev e r, if t h is b it is set, th en th e inp u t is d e term in ed to b e du al ch ann e l an d determ ined by the state of t h e ienb pi n. if t h e ienb pi n is lo w, th en t h e in pu t d e tection is d i rected to lib-a. if t h e ienb pi n i s hi gh , t h e i n put i s di rect e d t o li b - b . in ei t h er case, b it 4 d e term in es th e actual p o l arity o f th ese si g n a ls. bit 2 - 0 d e term i n es t h e in tern al laten c y of th e g a in d e tect fu nct i o n. whe n t h e lib - a , b pi ns are m a de act i v e, t h ey are typically us ed to cha n ge a n attenuator or gain stage. sin ce th is is prio r t o th e adc , th ere is a laten c y asso ciated with th e adc an d with th e settlin g of th e g a i n ch ang e . th is reg i ster allo ws t h e i n ternal d e lay of th e lib-a,b si gnal t o be pr og ram m ed. rev. pr b. 7 / 25/2002 49
preliminary technical data AD6635 memory map for outp ut port control regis t ers ch add ress in hex r e g i s t e r b i t wid t h co m m e n t s 08 por t a contr o l register 4 3: por t a e n able 2 - 1 : hb a sig n al in terleav ein g 11 all 4 channels 1 0 ch s 0 , 1 , 2 01 chs 0, 1 0 0 ch 0 0 : b y pass 09 por t b contr o l register 3 2: por t b e n able 1 : hb a sig n al in terleav ein g 1 chs 2, 3 0 ch 2 0 : b y pass 0a agc a contr o l r e gister 8 7- 5: output wor d l e ngth 111 4 bits 110 5 bits 101 6 bits 100 7 bits 011 8 bits 010 10 bits 001 12 bits 000 16 bits 4 : clip p i n g erro r 1 : main tain l e v e l o f clip p i n g erro r 0 : main tain o u t p u t sign al lev e l 3 : syn c n o w 2 : in it o n sy n c 1 : first s y n c o n l y 0 : b y p a ss 0b agc a hold off counter 16 15- 0: hold off value 0c agc a desir e d level 8 7- 0: desir e d output power level or clipping ener gy ( r par a m e ter) 0d agc a signal gain 12 11- 0: gs par a m e ter ( s et / m onitor) 0e agc a l oop gain 8 7- 0: k par a m e ter 0f agc a pole l o cation 8 7- 0: p param e ter 10 agc a average s a m p les 6 5-2: sc ale f o r ci c deci m a tor 1- 0: nu m b er of aver aging sam p les 11 agc a update decim a tion 12 11- 0: ci c deci m a tion r a tio 12 agc b contr o l r e gister 8 7- 5: output wor d l e ngth 112 4 bits 110 5 bits 102 6 bits 101 7 bits 011 8 bits 010 10 bits 001 12 bits 000 16 bits 4 : clip p i n g erro r 1 : main tain l e v e l o f clip p i n g erro r 0 : main tain o u t p u t sign al lev e l 3 : syn c n o w 2 : in it o n sy n c 1 : first s y n c o n l y 0 : b y p a ss 13 agc b hold off counter 16 15- 0: hold off value 14 agc b desir e d level 8 7- 0: desir e d output power level or clipping ener gy ( r par a m e ter) 15 agc b signal gain 12 11- 0: gs par a m e ter ( s et / m onitor) 16 agc b l oop gain 8 7- 0: k par a m e ter 17 agc b pole l o cation 8 7- 0: p param e ter 18 agc b ave r age s a m p les 6 5-2: sc ale f o r ci c deci m a tor 1- 0: nu m b er of aver aging sam p les 19 agc b update decim a tion 12 11- 0: ci c deci m a tion 1a par a llel a contr o l 8 7- 6: reser v ed 50 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 5 : parall el p o rt data fo r m at 1 : 8 - b i t pa rallel i, q 0 : 1 6 - b it i n terleav ed i, q 4 : ch an n e l 3 3 : ch an n e l 2 2 : ch an n e l 1 / agc b en ab le 1 : ch an n e l 0 / agc a en ab le 0 : agc_ c h select 1 : data co m e s f r o m agcs 0 : data co m e s f r o m ch an n e ls 1b l i nk a contr o l 8 7: l i nk por t a e n able 6 - 3 : wait 2 : no gain wo rd 1 : do n ? t o u tp u t g a in wo rd 0 : ou tp u t g a in wo rd 1 : ch an n e l data in te rleav ed 1 : 2 ch an n e l m o d e /sep arate ab 0 : 4 ch an n e l m o d e /ab sa m e p o r t 0 : agc_ c h select 1 : data co m e s f r o m agcs 0 : data co m e s f r o m ch an n e ls 1c par a llel b contr o l 8 7- 6: reser v ed 5 : parall el p o rt data fo r m at 1 : 8 - b i t pa rallel i, q 0 : 1 6 - b it i n terleav ed i, q 4 : ch an n e l 3 3 : ch an n e l 2 2 : ch an n e l 1 / agc b en ab le 1 : ch an n e l 0 / agc a en ab le 0 : agc_ c h select 1 : data co m e s f r o m agcs 0 : data co m e s f r o m ch an n e ls 1d l i nk b contr o l 8 7: l i nk por t b e n able 6 - 3 : wait 2 : no gain wo rd 1 : do n ? t o u tp u t g a in wo rd 0 : ou tp u t g a in wo rd 1 : ch an n e l data in te rleav ed 1 : 2 ch an n e l m o d e /sep arate ab 0 : 4 ch an n e l m o d e /ab sa m e p o r t 0 : agc_ c h select 1 : data co m e s f r o m agcs 0 : data co m e s f r o m ch an n e ls 1e por t clock contr o l 3 2- 1: pcl k divisor 0 : pclk ma ster/slav e 1 0 : slav e 1 : maste r 1 pcl k boots as slave. table 15. output p o rt control registers in orde r t o acc ess the output port registers the ?acce ss inpu t / ou tpu t co n t ro l reg i sters? b it (b it 5) in sleep reg i ster (0 x3) sh ou ld b e written h i gh . th e c a r (c h a n n e l add r ess reg i ster, ex tern al add r ess 0x6 ) is then written with th e address to t h e co rr ect output port r e gister. fo r ch ann e ls 0 to 3, halfb a nd filters a and b , agcs a and b an d out put p o rt s a a n d b , c h i p sel ect 0 (/ c s 0) s h o u l d be use d w h i l e pr o g ram m i ng usi n g m i crop ort . si m i l a rl y for ch ann e ls 4 t o 7, hal f b a nd f ilters c and d, agcs c and d and o u t p ut po r t s c an d d, c h i p sel ect 1 (/ c s 1) sh o u l d be use d w h i l e pr o g ram m i ng usi n g m i crop ort . no te: for all the reg i sters in the abo v e tab l e, o u t p u t po rts a a n d b (l i n k or pa ral l e l ) sh o u l d be d upl i cat ed wi t h out put ports c a n d d whe n c h ip sele ct 1 (/cs1) is used i n stead of (/cs0) wh ile prog ramm in g the micro p o r t. si milarly halfb a nd filters a and b, agcs a and b sho u l d b e d u p licated with halfb a nd c an d d, agcs c an d d resp ectiv ely. also ch ann e ls 0 to 3 sh ou ld b e d u p licated with ch ann e ls 4 to 7 wh erev er m e n tio n e d. 0 x08 po rt a co ntro l r e g i st er bit 0 en ab les t h e u s e o f in terp o l ating h a lf ban d filter cor r es po n d i n g t o p o rt a. hal f ba nd a can be use d t o in terleav e t h e d a ta stream s o f m u lt ip le ch ann e ls an d i n t e rp ol at e by t w o p r o v i d i n g a m a xim u m out put dat a rat e o f 4x t h e ch ip rate. it can b e co nfigu r ed t o listen to all four chan nel s ; c h an nel s 0, 1, 2 , 3; chan nel s 0, 1 , 2; cha n nel s 0, 1; o r o n l y cha n nel 0 . hal f ba nd a i s by pass ed whe n bi t 0 = 1 , in wh ich case th e ou tpu t s of th e rcfs are d i rectly sen t to th e agc. th e ch ann e l d a t a stream s still g e t in terleav e d with th e h a l f ban d b y p a ssed , b u t t h ey are not filtered and rev. pr b. 7 / 25/2002 51
preliminary technical data AD6635 in terpo l ated . th e m a x i m u m d a ta rate fro m th is co nf igu r ation w o u l d b e 2x t h e ch ip r a te. 0x09 p o rt b control re giste r bit 0 en ab les t h e u s e o f in terp o l ating h a lf ban d filter cor r es po n d i n g t o p o rt b . hal f ban d b can be use d t o in terleav e t h e d a ta stream s o f m u lt ip le ch ann e ls an d i n t e rp ol at e by t w o p r o v i d i n g a m a xim u m out put dat a rat e o f 4x t h e ch ip rate. it can b e co nfigu r ed t o listen to chan nel s 2 a n d 3; or o n l y cha nnel 2. hal f b a nd b i s by passe d w h en bi t 0 = 1, i n w h i c h ca se t h e o u t p ut s of t h e rcfs are d i rectly sen t to th e agc. th e ch an n e l d a ta stream s sti ll g e t in terleav ed with th e h a lf b a nd b y p a ssed , b u t t h ey are not filtered and interpo l ated . the m a x i m u m dat a rat e fr om thi s c o n f i g urat i o n w o ul d be 2 x t h e chi p rat e . 0x 0 a ag c a co ntr o l r e gis t er thi s 8- bi t re gi s t er co nt r o l s f eatu r e s of th e ag c a. th e b its are defi ne d bel o w: bi t s 7- 5 d e fi n e th e ou tpu t word leng th of t h e agc. th e out put w o r d ca n be 4- 8, 1 0 , 1 2 , o r 16 bi t s wi de. the cont rol regi st e r bi t re pre s ent a t i on t o obt ai n di ffe rent o u t p ut word leng th s is g i v e n i n the m e m o ry map table. b i t 4 o f t h i s re gi st er set s t h e m ode of o p erat i on f o r t h e agc. wh en t h is b it is 0, th e agc t r acks to main tain th e o u t p u t sign al lev e l and wh en th is b it is 1 , t h e agc track s to m a in tain a co n s tan t clipp i ng erro r. con s u l t th e agc sectio n for m o re d e tails abou t th ese m o d e s. th e b its 3-1 are u s ed t o co nf ig ur e t h e syn c hr on izatio n of th e agc. th e cic d ecim a to r filter in t h e agc can b e syn c hron ized to an ex tern al sy nc signal to output an updat e sam p le fo r t h e agc error cal cu latio n and filterin g . th is way t h e a g c gai n c h a nge s c a n be sy nch r o n i zed t o a n external bl ock like a rake rec e iver. whe n ever a n e x ternal sync signal is received, the hold off counter a t 0x0b is lo ad ed an d b e gin s to coun t dow n. w h en t h e co un ter reaches one t h e cic filter dum ps an update sam p le and starts wo rk ing to ward s a n e w u p d a te sam p le. th e agc can be initialized on each sy nc or only on the first sync. bit 3 is used to issu e a co mm a n d to t h e agc to sync im m e diately. if this bit is se t t h e cic filter will update the agc with a ne w sam p le im m e diately and start operati n g t o wa rds t h e ne xt u p d at e sam p l e . the a g c c a n be synchronized by the m i croport cont rol i n terface usi n g this m e t hod. bit 2 is used to d e term in e wheth e r t h e agc sh ou l d in itialize o n a sync or no t. wh en t h is b it is set, th e cic filter is cleared and n e w v a l u es fo r c i c d ecimatio n , num ber of ave r aging sam p les, cic scale, signal gai n ?gs ? , gain k a n d pol e pa ram e ter ?p? are loa d ed . whe n bit2 = 0 , t h e ab o v e-m e nt i oned pa ram e ters a r e not u p d a t e d an d t h e cic filter is n o t cleared . in both cases an agc up d a te sam p le is o u t pu t fro m th e cic filter and t h e d ecim a to r starts op erati n g to ward s th e n e x t ou tpu t sam p le wh en ev er a sy nc occ u rs. bit 1 is used to ig nore rep e titiv e sy n c hron izatio n si g n a ls. in som e appl i c at i ons, t h e sy n c hr o n i zat i on si gnal m a y occu r peri odically. if this bit is clear, each sync hronization requ est will re-syn chron i ze the agc. if t h is b it is set on ly th e first o c cu rren ce will cau se th e agc to sy n c hro n i ze and will u p d a te agc gain v a lu es p e riod ically d e p e nd ing o n th e d ecim a tio n factor o f th e agc cic filter. bit 0 is used to b y p a ss th e agc sectio n , wh en it is set. th e 2 3 -b it representatio n fro m in terp o l atin g h a l f b a nd filters is still red u c ed t o a lower b it wid t h rep r esen tatio n as set b y b its 7-5 of t h e agc a c o n t rol reg i ster. a tru n cation at th e ou tpu t o f the agc acco m p lish e s t h is task . 0x 0b ag c a hold o ff c o un ter th e agc a ho ld-off coun ter is lo ad ed with th e v a l u e written t o th is ad dress wh en eith er a soft_ s ync or pi n_ sy nc c o m e s i n t o t h e ch annel . t h e c o u n t e r be gi ns cou n t i n g do w n so w h en i t rea c hes o n e, a s y nc i s gi ve n t o agc a. th is sync m a y o r may n o t in itialize th e agc , as defi ned by t h e cont rol w o r d . the a g c l o op i s u p d at ed with a n e w sam p le fro m th e cic filter wh en ev er a sync o ccurs. if th is reg i ster is writt en to on e, th e agc will b e updated imme diately whe n t h e sync occurs. if this reg i ster is written to a zero th e agc can n o t be syn c hr on ized. 0x 0 c ag c a desired le vel thi s 8- bi t re gi s t er co nt ai ns t h e desi re d o u t p ut p o we r l e vel or desi red cl i p pi n g l e vel de pe ndi ng o n t h e m ode o f ope rat i o n. t h i s desi re d r e q u e s t ?r? lev e l can b e set in d b fr om 0 t o ?2 3. 99 i n st eps o f 0 . 0 9 4 d b . 8 - bi t b i nary fl oat i n g- poi nt re pre s ent a t i on i s use d w i t h 6 bi t m a nt i s sa an d 2- bi t exp o n ent . m a n t i ssa i s i n st ep s o f 0. 09 4 db a n d ex p one nt i n 6. 02 db st eps . 0x 0 d ag c a sign al g a in th is reg i ster is u s ed t o set th e in itial v a lu e for a sign al gain u s ed i n the g a in m u ltip li er. th is 12 -b it v a lu e sets th e in itial sig n a l gain b e t w een 0 an d 96 .29 6 d b i n step s o f 0. 02 4 d b . 1 2 - b i t bi na ry fl oat i n g - p oi nt re p r ese n t a t i on i s use d wi t h 8 bi t m a nt i ssa and 4- bi t ex p one nt . 0x 0e ag c a l oop g a i n thi s 8- bi t re gi s t er i s u s ed t o d e fi ne t h e ope n l o o p gai n ? k ?. it s val u e ca n b e set f r om 0 t o 0. 99 6 i n st e p s of 0 . 0 0 3 9 . t h i s v a lu e of ?k? is u p d a ted in t h e agc l o op each tim e th e agc is in itialized . 0 x 0 f agc a po le lo cat i o n th is 8 - b it reg i ster is used to defin e t h e o p e n lo op filter pol e l o cat i o n ? p ?. it s val u e ca n be set fr om 0 t o 0. 99 6 i n step s o f 0.003 9. th is v a l u e o f ? p ? is upd ated in th e ag c lo op each tim e th e agc is i n itialized . th is op en loo p po le 52 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 bit 2 is used to d e term in e wheth e r t h e agc sh ou l d in itialize o n a sync or no t. wh en t h is b it is set, th e cic filter is cleared and n e w v a l u es fo r c i c d ecimatio n , num ber of ave r aging sam p les, cic scale, signal gai n ?gs ? , gain k a n d pol e pa ram e ter ?p? are loa d ed . whe n bit2 = 0 , t h e ab o v e-m e nt i oned pa ram e ters a r e not u p d a t e d an d t h e cic filter is n o t cleared . in both cases an agc up d a te sam p le is o u t pu t fro m th e cic filter and t h e d ecim a to r starts op erati n g to ward s th e n e x t ou tpu t sam p le wh en ev er a sy nc occ u rs. lo catio n will d i rectly i m p act t h e closed loo p p o l e l o cation s as explaine d in the agc section. 0x 1 0 ag c a aver a g e s a m p les th is 6 - b it reg i ster con t ain s t h e scale u s ed fo r th e cic filter and the num b er of powe r sam p les to be ave r aged be fore b e ing fed to t h e cic filter. bits 5 - 2 d e fin e th e scale u s ed for th e cic filter. b i t s 1- 0 defi ne t h e num ber of sam p l e s t o be a v era g e d b e fo re th ey are sen t t o th e cic d ecim a t i n g filter. th is num ber ca n be set bet w ee n 1 a n d 4 wi t h bi t re prese n t a t i o n 00 m eani ng 1 s a m p l e and bi t r e prese n t a t i o n 1 1 m eani ng 4 sam p les. bit 1 is used to ig nore rep e titiv e sy n c hron izatio n si g n a ls. in som e appl i c at i ons, t h e sy n c hr o n i zat i on si gnal m a y occu r peri odically. if this bit is clear, each sync hronization requ est will re-syn chron i ze the agc. if t h is b it is set on ly th e first o c cu rren ce will cau se th e agc to sy n c hro n i ze and will u p d a te agc gain v a lu es p e riod ically d e p e nd ing o n th e d ecim a tio n factor o f th e agc cic filter. 0x 1 1 ag c a upd a te de cimati on th is 1 2 -b it register sets th e agc decim a tio n ratio fro m 1 to 409 6. a n app r op r i ate scalin g fact or should be set factor to avo i d lo ss of b its. bit 0 is used to b y p a ss th e agc sectio n , wh en it is set. th e 2 3 -b it representatio n fro m in terp o l atin g h a l f b a nd filters is still red u c ed t o a lower b it wid t h rep r esen tatio n as set b y b its 7-5 of t h e agc a c o n t rol reg i ster. a tru n cation at th e ou tpu t o f the agc acco m p lish e s t h is task . 0x 1 2 ag c b co ntr o l r e gis t er thi s 8- bi t re gi s t er co nt r o l s f eatu r e s of th e ag c a. th e b its are defi ne d bel o w: 0x 1 3 ag c b hold o ff c o un ter bi t s 7- 5 d e fi n e th e ou tpu t word leng th of t h e agc. th e out put w o r d ca n be 4- 8, 1 0 , 1 2 , o r 16 bi t s wi de. the cont rol regi st e r bi t re pre s ent a t i on t o obt ai n di ffe rent o u t p ut word leng th s is g i v e n i n the m e m o ry map table. th e agc a ho ld-off coun ter is lo ad ed with th e v a l u e written t o th is ad dress wh en eith er a soft_ s ync or pi n_ sy nc c o m e s i n t o t h e ch annel . t h e c o u n t e r be gi ns cou n t i n g do w n so w h en i t rea c hes o n e, a s y nc i s gi ve n t o agc a. th is sync m a y o r may n o t in itialize th e agc , as defi ned by t h e cont rol w o r d . the a g c l o op i s u p d at ed with a n e w sam p le fro m th e cic filter wh en ev er a sync o ccurs. if th is reg i ster is writt en to on e, th e agc will b e updated imme diately whe n t h e sync occurs. if this reg i ster is written to a zero th e agc can n o t be syn c hr on ized. b i t 4 o f t h i s re gi st er set s t h e m ode of o p erat i on f o r t h e agc. wh en t h is b it is 0, th e agc t r acks to main tain th e o u t p u t sign al lev e l and wh en th is b it is 1 , t h e agc track s to m a in tain a co n s tan t clipp i ng erro r. con s u l t th e agc sectio n for m o re d e tails abou t th ese m o d e s. th e b its 3-1 are u s ed t o co nf ig ur e t h e syn c hr on izatio n of th e agc. th e cic d ecim a to r filter in t h e agc can b e syn c hron ized to an ex tern al sy nc signal to output an updat e sam p le fo r t h e agc error cal cu latio n and filterin g . th is way t h e a g c gai n c h a nge s c a n be sy nch r o n i zed t o a n external bl ock like a rake rec e iver. whe n ever a n e x ternal sync signal is received, the hold off counter a t 0x0b is lo ad ed an d b e gin s to coun t dow n. w h en t h e co un ter reaches one t h e cic filter dum ps an update sam p le and starts wo rk ing to ward s a n e w u p d a te sam p le. th e agc can be initialized on each sy nc or only on the first sync. 0x 1 4 ag c b desired le vel thi s 8- bi t re gi s t er co nt ai ns t h e desi re d o u t p ut p o we r l e vel or desi red cl i p pi n g l e vel de pe ndi ng o n t h e m ode o f ope rat i o n. t h i s desi re d r e q u e s t ?r? lev e l can b e set in d b fr om 0 t o ?2 3. 99 i n st eps o f 0 . 0 9 4 d b . 8 - bi t b i nary fl oat i n g- poi nt re pre s ent a t i on i s use d w i t h 6 bi t m a nt i s sa an d 2- bi t exp o n ent . m a n t i ssa i s i n st ep s o f 0. 09 4 db a n d ex p one nt i n 6. 02 db st eps . 0x 1 5 ag c b si gn al g a i n th is reg i ster is u s ed t o set th e in itial v a lu e for a sign al gain u s ed i n the g a in m u ltip li er. th is 12 -b it v a lu e sets th e in itial sig n a l gain b e t w een 0 an d 96 .29 6 d b i n step s o f 0. 02 4 d b . 1 2 - b i t bi na ry fl oat i n g - p oi nt re p r ese n t a t i on i s use d wi t h 8 bi t m a nt i ssa and 4- bi t ex p one nt . bit 3 is used to issu e a co mm a n d to t h e agc to sync im m e diately. if this bit is se t t h e cic filter will update the agc with a ne w sam p le im m e diately and start operati n g t o wa rds t h e ne xt u p d at e sam p l e . the a g c c a n be synchronized by the m i croport cont rol i n terface usi n g this m e t hod. 0x 1 6 ag c b loop g a in thi s 8- bi t re gi s t er i s u s ed t o d e fi ne t h e ope n l o o p gai n ? k ?. it s val u e ca n b e set f r om 0 t o 0. 99 6 i n st e p s of 0 . 0 0 3 9 . t h i s rev. pr b. 7 / 25/2002 53
preliminary technical data AD6635 v a lu e of ?k? is u p d a ted in t h e agc l o op each tim e th e agc is in itialized . 0x 1 7 ag c b pole loc a tion th is 8 - b it reg i ster is used to defin e t h e o p e n lo op filter pol e l o cat i o n ? p ?. it s val u e ca n be set fr om 0 t o 0. 99 6 i n step s o f 0.003 9. th is v a l u e o f ? p ? is upd ated in th e ag c lo op each tim e th e agc is i n itialized . th is op en loo p po le lo catio n will d i rectly i m p act t h e closed loo p p o l e l o cation s as explaine d in the agc section. 0x 1 8 ag c b aver a g e s a m p les th is 6 - b it reg i ster con t ain s t h e scale u s ed fo r th e cic filter and the num b er of powe r sam p les to be ave r aged be fore b e ing fed to t h e cic filter. bits 5 - 2 d e fin e th e scale u s ed for th e cic filter. b i t s 1- 0 defi ne t h e num ber of sam p l e s t o be a v era g e d b e fo re th ey are sen t t o th e cic d ecim a t i n g filter. th is num ber ca n be set bet w ee n 1 a n d 4 wi t h bi t re prese n t a t i o n 00 m eani ng 1 s a m p l e and bi t r e prese n t a t i o n 1 1 m eani ng 4 sam p les. 0x 1 9 ag c b upd a te de cimati on th is 1 2 -b it register sets th e agc decim a tio n ratio fro m 1 to 409 6. a n app r op r i ate scalin g fact or should be set factor to avo i d lo ss of b its. 0 x1a pa ra llel po rt co ntro l a data is out put t h rough eithe r a pa rallel port interface or a link port inte rface. whe n 0x19 bit 7 = 0, the use of link p o rt a is d i sab l ed an d th e u s e o f p a rallel po rt a is en ab led. th e p a rallel p o rt prov id es d i fferen t d a ta m o des fo r interfaci ng wit h dsps or fp gas. bit 0 selects wh ich d a ta is ou tp u t on p a rallel p o rt a. wh en bi t 0 = 0 , paral l el po rt a o u t p ut s dat a f r om t h e r c f according t o the form at specifi ed by bits 1 through 4. wh en b it 0 = 1, p a rallel po rt a o u t p u t s th e data fro m th e agcs according to t h e form a t specified by bits 1 a n d 2. in agc m o d e , b it 0 = 1 an d bit 1 d e term in es if p a rallel po rt a i s a b l e t o out put dat a fr om agc a a n d bi t 2 d e term in es if parallel p o rt a i s ab le t o o u t p u t d a ta fro m agc b . the o r de r of o u t p ut depe n d s o n t h e rat e of trigge rs from each agc , whi c h in turn is de termined by t h e deci m a t i on rat e of t h e c h a nnel s fee d i n g i t . i n c h a nnel m ode, bi t 0 = 0 an d bi t s 1 t h r o ug h 4 det e rm i n e w h i c h com b i n at i on of t h e fo ur p r oce ssi ng cha n nel s i s o u t p ut . the output order depe nds on the rate of tri g gers receive d from each cha nnel, which is determ ined by the decim a tion rat e o f eac h c h annel . t h e c h a nnel o u t p ut i n d i cat or pi ns can be use d t o det e rm i n e whi c h dat a cam e fr om whi c h channel. bit 5 d e term in es th e form at o f th e ou tpu t d a ta wo rd s. wh en b it 5 = 0, p a rallel po rt a o u t p u t s 16 -bit word s on its 1 6 -b it bu s. this m ean s th at i an d q d a ta are in terleav ed and t h e i q i n di cat or pi n det e rmines whether data on t h e p o rt is i d a ta or q d a ta. wh en b it 5 = 1 , p a rallel p o rt a is o u t p u tting an 8-b it i word and an 8-b it q word at th e sam e ti m e , an d t h e iq ind i cator p i ns will b e high. 0x 1b l i nk p o rt con t r o l a data is out put t h rough eithe r a pa rallel port interface or a link port inte rface. t h e link po rt provi des a n e fficient data l i nk bet w ee n t h e ad 6 6 3 5 a n d a ti ger s h a r c dsp an d can b e en ab led b y setting b it 7 = 1 . bit 0 selects wh ich d a ta is ou tp u t on link p o rt a. wh en b it 0 = 0 , link port a out puts data from the rcf according t o th e fo rm at sp ecified b y b it 1 . wh en b it 0 = 1 , link po rt a out puts the dat a from the agcs accordi n g to the form at speci fi ed by bi t s 1 a n d 2. b i t 1 has t w o d i ffere nt m eani ngs t h at de pe nd on w h et he r d a ta is co m i n g fro m th e agc s or fro m th e rcfs. when d a ta is co m i n g fro m th e rcfs (b it 0 = 0), b it 1 selects bet w ee n t w o a n d f o ur c h a nne l dat a m ode. b i t 1 = 1 in d i cates link po rt a tran sm its rcf iq word s altern ately fr om channel s 0 a n d 1 . wh en bi t 1 = 1, l i n k po rt a out put s rcf iq words from each of the four c h annels in successi on: 0, 1, 2, t h e n 3. h o we ve r, w h en agc dat a i s selected (b it 0 = 1), b it 1 selects th e agc d a ta o u t p u t m ode. i n t h i s m ode, w h en bi t 1 = 1, l i n k p o r t a o u t p ut s agc a i q a n d gain w o rds . w i t h this m ode, gai n wor d s m u st b e in cluded b y settin g b i t 2 = 0 . howev e r, if b it 0 = bi t 1 = 0 , t h e n agc a a n d b are al t e r n at el y out put o n l i n k po rt a a n d t h e i n cl usi o n or ex cl usi o n of t h e gai n w o r d s i s d e term in ed b y b it 2 . bit 2 selects if g a in wo rd s are in clu d e d or n o t in th e d a ta out put . if bi t 1 = 1, bi t 2 = 0 . si nce t h e gai n wo rd s ar e onl y t w o by t e s l o n g a n d t h e i q wo rd s are f o ur by t e s l o n g , the gai n words are padde d with ze ros to give a full 16-byte ti gers h a r c qua d - w o r d . if agc o u t p ut i s not sel ect ed (b it 0 = 0 ) th en th is b it can b e an y v a l u e. bits 6 thr oug h 3 sp ecif y th e pr og r a mm ab le delay v a lu e f o r lin k p o rt a b e tween th e tim e t h e link p o rt receiv es a d a ta ready from the receiver a n d th e tim e it transmits the first data w o rd. t h e link port m u st wait at least 6 cycles of the receiver?s cl oc k, s o t h is value allows the use r to use cloc ks of di f f eri n g f r e que ncy a n d p h a se f o r t h e a d 6 6 3 5 l i n k po rt an d th e tig e rsharc link port. th ere is m o re inform atio n o n th e lim ita tio n s and relationsh i p of th ese cl o c ks in th e sectio n on li nk po r t s. 0 x1c pa ra llel po rt co ntro l b data is out put t h rough eithe r a pa rallel port interface or a link port inte rface. whe n 0x1b bit 7 = 0, the use of link p o rt b is d i sab l ed an d th e u s e o f p a rallel po rt b is en ab led. th e p a rallel p o rt prov id es d i fferen t d a ta m o des fo r interfaci ng wit h dsps or fp gas. 54 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 bit 0 selects wh ich d a ta is ou tp u t on p a rallel p o rt b. wh en bi t 0 = 0 , paral l el po rt b o u t p ut s dat a f r om t h e r c f according t o the form at specifi ed by bits 1 through 4. wh en b it 0 = 1, p a rallel po rt b ou tpu t s th e data fro m th e agcs according to t h e form a t specified by bits 1 a n d 2. in agc m o d e , b it 0 = 1 an d bit 1 d e term in es if p a rallel po rt b i s a b l e t o out put dat a fr om agc a a n d bi t 2 d e term in es if parallel p o rt b i s ab le t o o u t p u t d a ta fro m agc b . the o r de r of o u t p ut depe n d s o n t h e rat e of trigge rs from each agc , whi c h in turn is de termined by t h e deci m a t i on rat e of t h e c h a nnel s fee d i n g i t . i n c h a nnel m ode, bi t 0 = 0 an d bi t s 1 t h r o ug h 4 det e rm i n e w h i c h com b i n at i on of t h e fo ur p r oce ssi ng cha n nel s i s o u t p ut . the output order depe nds on the rate of tri g gers receive d from each cha nnel, which is determ ined by the decim a tion rat e o f eac h c h annel . t h e c h a nnel o u t p ut i n d i cat or pi ns can be use d t o det e rm i n e whi c h dat a cam e fr om whi c h channel. bit 5 d e term in es th e form at o f th e ou tpu t d a ta wo rd s. wh en b it 5 = 0, p a rallel po rt b ou tpu t s 16-bit word s on its 1 6 -b it bu s. this m ean s th at i an d q d a ta are in terleav ed and t h e i q i n di cat or pi n det e rmines whether data on t h e p o rt is i d a ta or q d a ta. wh en b it 5 = 1 , p a rallel p o rt b is o u t p u tting an 8-b it i word and an 8-b it q word at th e sam e ti m e , an d t h e iq ind i cator p i ns will b e high. 0 x1d link port co ntro l b data is out put t h rough eithe r a pa rallel port interface or a link port inte rface. t h e link po rt provi des a n e fficient data l i nk bet w ee n t h e ad 6 6 3 5 a n d a ti ger s h a r c dsp an d can b e en ab led b y setting b it 7 = 1 . bit 0 selects wh ich d a ta is ou tp u t on link p o rt b. wh en b it 0 = 0 , link port b outputs data from the rcf according t o th e fo rm at sp ecified b y b it 1 . wh en b it 0 = 1 , link po rt b out puts the dat a from the agcs accordi n g to the form at speci fi ed by bi t s 1 a n d 2. b i t 1 has t w o d i ffere nt m eani ngs t h at de pe nd on w h et he r d a ta is co m i n g fro m th e agc s or fro m th e rcfs. when d a ta is co m i n g fro m th e rcfs (b it 0 = 0), b it 1 selects bet w ee n t w o a n d f o ur c h a nne l dat a m ode. b i t 1 = 1 in d i cates link po rt a tran sm its rcf iq word s altern ately fr om channel s 0 a n d 1 . wh en bi t 1 = 1, l i n k po rt b out put s rcf iq words from each of the four c h annels in successi on: 0, 1, 2, t h e n 3. h o we ve r, w h en agc dat a i s selected (b it 0 = 1), b it 1 selects th e agc d a ta o u t p u t m ode. i n t h i s m ode, w h en bi t 1 = 1, l i n k p o r t b o u t p ut s agc b i q a n d gain w o rds . w i t h this m ode, gai n wor d s m u st b e in cluded b y settin g b i t 2 = 0 . howev e r, if b it 0 = bi t 1 = 0 , t h e n agc a a n d b are al t e r n at el y out put o n l i n k po rt b a n d t h e i n cl usi o n or ex cl usi o n of t h e gai n w o r d s i s d e term in ed b y b it 2 . bit 2 selects if g a in wo rd s are in clu d e d or n o t in th e d a ta out put . if bi t 1 = 1, bi t 2 = 0 . si nce t h e gai n wo rd s ar e onl y t w o by t e s l o n g a n d t h e i q wo rd s are f o ur by t e s l o n g , the gai n words are padde d with ze ros to give a full 16-byte ti gers h a r c qua d - w o r d . if agc o u t p ut i s not sel ect ed (b it 0 = 0 ) th en th is b it can b e an y v a l u e. bits 6 thr oug h 3 sp ecif y th e pr og r a mm ab le delay v a lu e f o r lin k p o rt b b e t w een th e tim e t h e link p o rt receiv es a d a ta ready from the receiver a n d th e tim e it transmits the first data w o rd. t h e link port m u st wait at least 6 cycles of the receiver?s cl oc k, s o t h is value allows the use r to use cloc ks of di f f eri n g f r e que ncy a n d p h a se f o r t h e a d 6 6 3 5 l i n k po rt an d th e tig e rsharc link port. th ere is m o re inform atio n o n th e lim ita tio n s and relationsh i p of th ese cl o c ks in th e sectio n on li nk po r t s. 0x 1e p o r t cl o c k c o n t rol bit 0 d e term in es wh eth e r pc lk is supp lied ex tern ally b y th e user or d e ri v e d in tern ally in th e ad6 635 . if pclk is d e ri v e d in tern ally fro m clk (bit 0 = 1 ) , it is o u t p u t th ro ugh th e pc lk p i n as a m a ster cloc k. for m o st ap p lication s , pclk will b e p r o v i d e d b y t h e u s er as an in pu t to t h e ad 663 5 v i a t h e pclk p i n. b i t s 2 an d 1 al l o w t h e use r t o di vi de c l k by an i n t e ge r v a lu e t o g e ner a te pclk (0 0 = 1 , 01 = 2, 1 0 = 3 , 11 = 4) . microport cont rol th e ad 663 5 has an 8- b it m i c r op ro cessor p o r t and t w o serial control port. t h e use of each of these ports is d e scri b e d sep a rately b e low. th e i n teraction of th e po rts is th en d e scrib e d . th e micro p o r t in terface is a m u l ti- m o d e in terface th at i s d e si g n e d t o giv e flex ib ility wh en d ealing with th e ho st pro cessor. t h ere are t w o m odes of bus o p e ration : in tel no n-m u ltip lex e d m o d e (inm ), and m o t o r o l a no n - m u lt i p l e xed m ode (m nm ). the m ode i s sel ect ed bas e d on h o st pr oces sor an d w h i c h m ode i s best sui t e d t o t h at p r oces so r. the m i cro-p o r t has an 8- bi t dat a bus ( d [ 7 : 0 ] ) , 3- bi t ad dres s bus (a [2: 0 ] ) , 4 c o n t rol pi ns l i n es (/cs0, /cs1, / d s or /rd, rw or / w r) , a n d one status p i n(dtac k o r rdy). th e fun c tio n a lity of t h e co n t ro l si gnal s a n d st at us l i n e cha n ges sl i ght l y de pe n d i n g up o n t h e m o d e th at is cho s en . refer to th e tim in g d i ag ram s an d th e fo llowing d e scrip tion s for d e tails o n th e op eratio n o f bo th m odes. external me mor y map the e x ternal me m o ry map i s use d t o gain access to t h e channel addre ss space a n d inpu t / out put address space descri bed p r e v i ousl y . t h e 8- b i t dat a an d a d d r ess bu ses a r e u s ed to th is set of 8 reg i sters th at can b e seen in th e following ta ble 16. t h ese registers are c o lle ctively refe rre d to as t h e e x ternal int e rface re gisters since t h ey cont rol all acce sses to t h e c h a nnel address s p ace as well as input / out p ut chi p functio ns. t h e use of each of these rev. pr b. 7 / 25/2002 55
preliminary technical data AD6635 i ndi vi dual re gi st ers i s descri b e d bel o w i n det a i l . it s h o u l d be note d that the se rial control interface has the sam e m e mo r y ma p a s t h e mi c r o - p o r t interface and can ca rry out th e exact same fun c tio n s , alt h o ugh at a slow er r a te. a [ 2 : 0 ] n a m e co m m e n t 111 access control re gister (acr) 7: auto inc r e m e n t 6: br oadcast 5: unused bit 4- 2: i n str u ction[2: 0] 1- 0: a[9:8] 110 channel addr ess register (car) 7- 0: a[7:0] 101 soft _sync contr o l register (writ e only ) 7 : pn_ e n 6 : t e st_ m ux_ s e lect 5: hop 4 : sta r t 3 : sy ncd 2 : sy ncc 1 : sy ncb 0 : sy nca 100 pi n_sync control register (writ e only ) 7: t oggle ie n fo r bi st 6 : fi rst sy nc o n ly 5: hop_e n 4 : sta r t_ en 3: sync_e n 3 2: sync_e n 2 1: sync_e n 1 0: sync_e n 0 0 1 1 s l e e p (writ e only ) 7- 6: reser v ed 5: access i nput/output por t contr o l register s 4 : rese rv ed lo w 3 : s l e e p 3 2 : s l e e p 2 1 : s l e e p 1 0 : s l e e p 0 010 data register 2 (dr2) 7- 4: reser v ed 3- 0: d[19:1 6 ] 001 data register 1 (dr1) 15- 8: d[15: 8] 000 data register 0 (dr0) 7- 0: d[7:0] the e x ternal address s p ace defi ned by t h e eight registers can be treate d as two a d dre ss spaces with ea ch a d dress space ha ving its own chi p sele ct pins (/cs0 a n d /cs1). for pr o g ram m i ng t h r o ug h m i crop ort c h a nnel s 0 t o 3, i n p u t po rt s a a n d b , hal f ban d a n d agc s a an d b an d out put p o r t s a an d b, /cs0 sh ou ld b e u s ed . for pr ogr ammin g t h r o u g h m i cropo rt c h an nel s 4 t o 7, i n p u t po r t s c an d d, hal f ban d a n d agc s c an d d an d out put p o r t s c an d d, /cs1 s h ould be use d . th ou g h onl y e x t e r n al ad dr ess m a p corre sp o ndi ng t o / c s 0 is explained in this datas h eet, at all places it shoul d also be rep l aced b y /cs1 t o co m p lete th e fun c tion a lity. w h en t h is i s d one , c h an n e l s 0 t o 3 s h o u l d be repl ace d b y chan nel s 4 to 7, input / out put ports a a n d b s h oul d be replaced by in pu t / ou tpu t po rts c and d resp ectiv ely, an d halfb a n d / agcs a and b shoul d be repl aced by hal f ba nd / agcs c and d res p ectively. access control regis t er(acr) the access control register s e rves to de fine the cha n nel or cha n nels tha t receive a n ac cess from the micro-port or serial p o rt c o ntrol. bit 7 of th is reg i ster is t h e auto -in c rem e n t b it. if th is b it is a 1 t h en th e c a r reg i ster d e scrib e d b e low will in crem en t its value a f ter e v ery acces s to the c h annel. t h is allows bloc ks of address spa ce s u ch as coe fficient me m o ry to be in itialized m o re efficien tly. ta bl e 1 6 . ext e rnal mem ory ma p micropor t ins t ructi o ns i n s t r u c t i o n c o m m e n t : 0000 all chips and all channels will get t h e access. 0001 channel 0,1,2 of al l chips will get the access. 0010 channel 1,2,3 of al l chips will get the access. 0100 all chips will get t h e access. 1 1000 all chips with chip_id[3:0] = xxx0 will get the access. 1 1001 all chips with chip_id[3:0] = xxx1 will get the access. 1 1100 all chips with chip_id[3:0] = xx00 will get the access. 1 1101 all chips with chip_id[3:0] = xx01 will get the access. 1 1110 all chips with chip_id[3:0] = xx10 will get the access. 1 1111 all chips with chip_id[3:0] = xx11 will get the access. 1 bit 6 of th e reg i ster is t h e bro a dcast b it and determ in es ho w b its 5-2 are in t e rpreted . if b r o a d c ast is 0 t h en bits 4-2 , wh ich ar e r e f e r e ed to as instru ction b i ts (in stru ction[2 : 0 ]), ar e com p are d wi t h t h e c h ip _ i d[ 2: 0] pi ns. t h e i n s t ru ct i o n w h i c h m a tches the c h ip_id[2: 0 ] pins will dete rm ine the access. t h i s a l lo ws u p to 8 ch i p s to b e co n n e c t ed to th e s a me p o r t a n d m e m o ry m a ppe d wi t h out e x t e r n al l o gi c. t h i s al so al l o w s t h e sam e ser i al por t of a ho st pro c essor t o co nf i g u r e up to 8 ch i p s. if t h e b r oa dcast bi t i s hi g h t h e i n st r u ct i o n [ 2: 0] w o r d al l o w s m u ltip le AD6635 ch ann e ls and/o r ch i p s t o be con f i gured si m u l t a neo u sl y i n de pe nd ent of t h e c h ip _ i d[ 2: 0] pi ns. t h er e are 1 0 po ssi bl e i n st r u ct i o ns t h at are d e fi ne d i n t h e t a bl e bel o w. th is is usefu l for sm art an tenn a system s wh ere m u ltip le ch ann e ls listing to a si ng le an tenn a or car r i er can be conf igur ed s i mu l t a n e o u s l y. th e x ? s in th e ta b l e r e p r e s e n t d o n ? t c a r e s i n t h e di gi t a l dec o di ng . 1 a[ 9: 8] bi t s co nt r o l w h i c h ch annel i s dec o d e d fo r t h e access. ta bl e 1 7 . mi cr op ort inst r u ct i ons whe n b r oa dca s t i s ena b l e d ( b i t 6 set hi g h ) re ad back i s not v a lid b ecau s e o f th e po ten tial fo r i n tern al bus con t en tion . there f ore, if re ad back is s u bs eque ntly desi re d, t h e b r o a d cast b it sh ou ld b e set low. external me mor y map 56 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 b i t s 1- 0 of t h i s re gi st er are a d dress bi t s t h at deco de w h i c h of the four c h a nnels are bei ng accessed. if the inst ruction bits dec o de a n access to m u ltiple cha n nels then the s e bits are ignore d. if the inst ruction dec ode s a n ac cess to a su bset of ch ip s th en th e a[9 : 8] b its will o t herwise determ ine the channel being accessed. ch annel ad dr ess re gister ( c a r ) this register re prese n ts t h e 8-bit internal address of each ch ann e l. if the au to-in c rem e n t b it o f th e acr is 1 t h en th is v a l u e will b e in crem en ted after ev ery access to t h e dr0 re gister, whic h will in t u rn access the location poi nt ed t o by t h i s a d d r ess. t h e c h an nel ad dress re gi st er can no t b e read b ack wh ile th e bro a d cast b it is set h i g h . soft_sync c o nt ro l reg i st er ex tern al add r ess [5 ] is th e soft_ s ync co ntro l reg i ster an d is w r ite only. bit 0 - 3 of t h is reg i ster are t h e soft_sync co n t ro l b its. th ese p i ns m a y b e written t o b y th e con t ro ller to in itiate t h e sy nc hr o n i zat i on of a sel e c t ed cha n nel . a l t hou g h t h e r e are 4 inpu ts, these do no t n ecessarily go to the ch an n e l of th e sam e n u m b e r. th is is fu lly co nfigu r ab le at th e chann e l lev e l as to wh i c h b it to look at. all 4 ch ann e ls m a y b e co nf igu r ed t o syn c hr on ize fro m a si ngl e p o si t i on, o r t h ey m a y be pai r e d or al l i nde pe nd ent . bit 4 d e term in es if th e syn c h r o n i zation is t o ap p l y to a ch ip start. if t h is b it is set, a ch ip st art will b e in itiated . bit 5 d e term in es if th e syn c h r o n i zation is t o ap p l y to a ch ip h o p . if t h is b it is set, th e nc o freq u e n c y will b e up d a ted whe n t h e whe n the soft_sync occurs. bit 6 con f i g ures ho w th e in tern al d a ta bu s is co nfigu r ed . if th is b it is set l o w, t h en th e i n t e rn al adc d a t a bu ses are co nfigu r ed no rmall y . if th is bit is set, th en the in tern al test signals a r e sele cted. the internal test signals are co nfigu r ed i n bit 7 of th is reg i ster. bit 7 if set clear, a n e g a tiv e full scale sig n a l i s g e n e rated an d m a d e av ailab l e to t h e i n tern al d a ta b u s . if t h is b it is hi g h , t h en i n t e r n al p s eu d o ra nd om seque nce g e nerat o r i s en ab led an d th i s d a ta is av ailab l e to t h e i n tern al d a ta bu s. th e co m b in ed fun c tion s o f b i t 6 and 7 facilit ate v e rification o f a g i v e n filter desig n . also, in con j un ction with th e misr reg i sters allows fo r d e tailed i n -system ch ip testin g . in co nj un ction with t h e jtag test bo ard , v e ry hi g h l e vel s o f c h i p ve ri fi cat i o n can be d one d u ri ng sy st em test, both i n the factory and fi eld. pin_ sy nc co ntro l r e g i st er ex tern al add r ess [4 ] is th e pi n_ sy nc c ont rol regi st er an d is w r ite only. bit 0 - 3 of t h is reg i ster are t h e sync _ e n con t ro l b its. th ese p i ns m a y b e written t o b y th e con t ro ller to allo w p i n synchronization of a selected channel. alt h ough t h ere are 4 inpu ts, t h ese d o no t n ecessarily g o to t h e ch ann e l o f th e sam e n u m b e r. th is is fu lly con f i g urab le at the ch an n e l lev e l as to wh i c h b it to look at. all 4 ch ann e ls m a y b e co nf igu r ed t o syn c hr on ize fro m a si ngl e p o si t i on, o r t h ey m a y be pai r e d or al l i nde pe nd ent . unl i k e t h e sy nc pi ns , sy nc _e n a r e di f f ere n t f o r c h an nel s 0 t o 3 and cha n nel s 4 to 7. bit 4 d e term in es if th e syn c h r o n i zation is t o ap p l y to a ch ip start. if t h is b it is set, a ch ip st art will b e in itiated wh en th e pin_s y nc oc curs . bit 5 d e term in es if th e syn c h r o n i zation is t o ap p l y to a ch ip h o p . if t h is b it is set, th e nc o freq u e n c y will b e up d a ted whe n t h e whe n the p i n_ sy n c occ u rs . bit 6 is used to ig nore rep e titiv e sy n c hron izatio n si g n a ls. in so m e ap p licatio n s , th is si gn al m a y o ccu r p e ri o d i cally. if this bit is clear, each pin_ sync will re start/hop the ch ann e l. if th i s b it is set, th en o n l y th e first o ccurren ce will cau se t h e ch ip t o take act io n . bit 7 is used with b it 6 and 7 o f ex tern al address 5 . wh en th is b it is cleared , t h e d a ta sup p lied to t h e i n tern al d a ta bu s si m u lates a no rmal adc. when th is b it is set, th e d a ta su pp lied is in t h e form o f a ti me m u ltip lex e d adc su ch as th e ad6 600 (th i s allows th e eq u i v a len t o f testin g i n th e 4 ch ann e l inpu t m o d e ). in tern ally , wh en set, th is b it forces th e ien p i n to to gg le as if it were driv en b y th e a/b sign al o f th e ad 660 0. sleep co ntro l reg i ster ex tern al add r ess [3 ] is the sleep register. bits 3 - 0 co n t rol th e state of each o f th e ch an nels. each b it cor r es po n d s t o one o f t h e pos s i bl e r sp c h a n nel s wi t h i n t h e device. if t h is bit is cleare d , t h e c h annel ope r ates n o rm all y . howev e r, wh en this b it is set, t h e in d i cated channel e n ters a low power sleep m ode. bit 4 is reserv ed an d sh ou ld be set to 0 al ways. bit 5 allo ws access to t h e inpu t/ou t p u t c o n t ro l port reg i sters at chan n e l add r esses 00 -1 e. when th is b it is set low, the norm al m e m o ry m a p is accessed. howe ve r, when this bit is set, it allows access to the input/output port control re gisters. acce ss to these re gisters allows t h e lo w e r an d upper thr e sh o l d s t o b e set al o n g w ith d w ell time as well as t h e halfb a nd , agc, ou tpu t p o rt (p arallel / lin k ) featu r es to b e co nfigu r ed . when th is b it is set, th e v a lu e in exter n al ad d r es s 6 (car ) poi n t s to the m e m o ry m a p fo r t h e i n put / o ut p u t p o rt c ont rol r e gi st ers i n st e a d of t h e no rm al channe l m e m o ry m a p. bit 6 - 7 a r e r e s e r v ed and sh ou ld b e s e t lo w. rev. pr b. 7 / 25/2002 57
preliminary technical data AD6635 data address regis t ers ex tern al add r ess [2 -0 ] fo r m th e d a ta r e g i sters d r 2 , d r 1 and dr 0 res p e c t i v el y . al l i n t e rnal dat a wo r d s ha ve wi dt hs that are less than or equal to 20 bits. acces ses to external address [0] dr0 trigge r a n i n ternal access t o the AD6635 base d on the a d dress i n dicated in the acr a n d car. t h us d u ring writes t o th e in tern al reg i sters, ex tern al add r ess [0] dr0 m u st b e written last. at th is po in t d a t a is transferred to th e i n tern al me m o ry in d i cated in a[9 : 0 ] . read s are per f o r m e d i n t h e op p o si t e di r ection. once t h e a d dress is set, ex tern al ad dress [0 ] dr 0m u s t b e th e fi rst d a ta reg i ster read to i n itiate an in tern al access. dr 2 is on ly 4 b its w i d e . d a ta written to th e upper 4 b its of th is reg i ster w ill b e igno red . li k e wise read ing fro m th is reg i ster will pr o duce o n l y 4 lsb s . write se quen c ing writing to an in tern al lo cation is ach i ev ed by first writin g th e upp er two b its of th e address to b its 1 thro ugh 0 o f th e acr. bits 7 : 2 m a y b e set to select th e ch ann e l as in d i cated above. th e c a r is th en written with th e low e r eig h t b its of t h e in tern al address (it d o e sn?t matter if th e car is written b e fore th e ac r as lon g as both are written before the i n ternal access ) . data register 2,(dr2) a n d reg i ster 1 (dr 1 ) m u st b e written first b ecau s e th e write to data re gister dr0 trigge rs the internal access . data reg i ster dr 0 m u st always b e th e last reg i st er written to in itiate th e in tern al write. read se quenc ing reading from the m i cro port is accom p lished in the sam e manner. t h e i n ternal address is set up t h e sa me way as the write. a read fro m d a ta reg i ster dr0 activ at es th e i n ternal read, thu s reg i ster dr 0 m u st always b e read first to in itiate an in tern al read fo llowed b y dr1 a nd dr 2 . th is prov id es th e 8 lsbs of t h e in tern al read thro ugh th e micro po rt (d [7: 0 ] ) . a d di t i onal dat a re gi st ers ca n be rea d t o rea d t h e b a lan ce of th e in tern al m e m o ry. rea d /write c h ainin g the m i cro port of the AD6635 allows for m u ltiple accesse s while /csn is held low. t h e user ca n access m u ltiple l o cat i ons by p u l si ng t h e / w r or / r d l i n e a n d c h an gi n g t h e conte n ts of t h e external three bit addres s bus . e x ternal access to t h e e x ternal re gisters of ta ble 13 is accom p lished in on e of two m o d e s u s ing t h e /cs0 , /cs1 , /rd, / w r , an d mode inputs . the access m odes a r e intel non- mu ltip lex e d mo d e and m o toro la non - m u ltip lex e d m o d e . these m odes a r e c ontrolled by the mode i n put (m o d e=0 f o r inm , m o de= 1 fo r m n m ) . /cs0, /cs 1 , /rd, a n d / w r cont rol t h e acc ess type for ea ch m ode. intel no n- mul t iplexed m o de (i nm ) mode m u st be tied low t o operate t h e AD6635 microprocess o r in inm m ode . t h e acces s type is co n t ro lled b y t h e u s er with the /cs0 , /cs1 , /rd (/ ds), and /w r (r w) i n p u ts. the rd y (/dt ack ) si g n al is pr o duce d by t h e m i cro po rt t o com m uni cat e t o t h e use r t h at an access ha s been c o m p leted. rdy (/dt ack) goes l o w at the start of the access and i s release d whe n the internal cycle is com p lete. see t h e ti ming dia g ram s for both t h e read and write m odes in the specifications. moto ro l a non-multiplex e d mode (mnm) mode m u st be tied hi gh to operate t h e AD6635 microprocess o r in mnm m o de. t h e acce ss t y pe is co n t ro lled b y t h e u s er with the /cs0 , /cs1 , /ds (/rd), and r w (/ wr) i n p u ts. the /dt a ck (r dy ) si g n al is pr o duce d by t h e m i cro po rt t o com m uni cat e t o t h e use r t h at an access ha s been c o m p leted. /dt a ck (r dy) goe s low whe n a n i n ternal access is c o m p le te and the n will return h i gh after /ds (/rd) is d e -asserted . see th e ti min g diagram s for both t h e read and write m odes in the specifications. serial p o rt control th e ad 663 5 has a two ser i al p o r t s ser v i n g as a co n t ro l interface apa r t from the m i cropo rt c ontrol i n terface. se rial port input pin (sdi0) ca n acce ss all of the int e rnal registe r s fo r t h e cha n nel s 0 t o 3, i n put / o u t p ut p o r t s a an d b , halfband / agcs a a n d b, and has preem ptive access ove r the m i croport. sim ilarly sdi4 can acc ess all of the i n ternal reg i sters fo r the ch an n e ls 4 to 7 , inp u t / ou tpu t ports c an d d, halfba nd / agcs c and d, and has pree m p tive access ove r t h e m i cropo rt . in t h i s m a nne r, a si n g l e dsp co ul d be u s ed to con t ro l th e ad66 35 ov er the se rial port c o ntrol in terface. the serial c ont rol p o rt uses t h e serial cloc k (sclk0 and sclk 4). t h e serial i n p u t p o rt is self -f ram i ng as descri bed bel o w a n d allows m o re efficient use of the seri al i npu t band w i dth fo r pr og r a m m in g . th e b e gin n i ng of a serial in pu t fra m e is sig n a led by a fram e bit that appears o n th e sdi p i n. th is is th e msb of th e serial inpu t fram e. after th e frame b it h a s b e en sam p led h i gh on th e falling edg e o f sclk a state coun ter will start and en ab le an 11 bit serial shift e r 4 se rial clock cycles later. t h ese 4 sclk cycles represe n t the ? d on?t care? bi ts of the serial fram e that are ignore d. afte r all o f th e b its are sh ifted th en t h e serial inpu t po rt will p a ss al o n g t h e 8 - b it d a ta and 3- bi t ad dre ss t o t h e ar bi t r at i o n bl oc k. th e serial word stru cture for th e sdi i n pu t is illu strated in th e figu re 4 8 b e low. on ly 1 5 b its are listed so t h at th e seco nd bi t i n a st anda rd 1 6 - bi t serial word is considere d th e fr ame b it. th e sh ifting o r d e r b e g i ns with frame an d sh ifts th e add r ess msb first an d th en t h e d a ta msb first. effectively sdi0 and sclk0 can program every register t h at can ot her w i s e be pr og ra m m e d usi n g / c s0 o n t h e m i crop ort . si m i l a rl y sdi 4 a n d sc l k 4 ca n pr o g ram every 58 rev. pr b. 7 / 25/2002
preliminary technical data AD6635 regi st er t h at ca n ot he rwi s e be pr o g ram m ed usi n g / c s1 o n the m i croport. t ssi t hsi sclk sdi data serial p o rt ti ming specific a ti ons the AD6635 s e rial control cha nnel ca n operate only in the sl ave m ode ( s c l k s h o u l d be su ppl i e d by t h e pr o g ram m i ng devi ce ). t h e di agram s bel o w i ndi cat e t h e requ ired tim in g for each o f the sp ecification . fig u r e 47 . s e ria l in pu t d a t a tim i ng requ irem en ts t sclk t sclkl t sclkh sclk sdi 0 , sdi4 sdi is th e serial data inp u t . serial data is sa m p led on t h e fal l i ng e d ge of sc lk. t h i s pi n i s use d i n t h e seri al co nt r o l m o d e to write th e in tern al cont r o l r e g i ster s of th e a d 66 35 . fi gure 4 3 . sc lk ti mi ng req u i r eme n t s sclk 0, scl k 4 sclk is a clo c k inpu t and t h e sdi inpu t is sa m p led on t h e fal l i ng e d ge of sc lk a n d al l out put s are swi t ched o n t h e ri si ng ed ge o f sc lk. t h e m a xi m u m speed of t h i s po rt i s 80m hz. scl k cl k t ds c l k h t sc l k l t sc l k h fi gure 4 6 . sc lk sw i t c hi n g c har act e ri st i c s ( d i v i d e by 1) fram e x x x x a 2 a 1 a 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sd i0 sc lk0 t ss i clkn fra m e x sc l k 4 sd i4 fi gure 4 8 . se ri al w o rd st r u ct ure a n d seri al port c ont r o l t i mi ng jtag boundary s can th e ad 663 5 su ppo r t s a su b s et o f i e ee stan d a rd 1 149 .1 sp ecification . fo r ad d ition a l d e tails o f th e stan d a rd , p l ease see ?iee e sta nda rd test acc e ss port a n d b o undary-scan arc h itecture , ? ieee -1149 publication from ieee. th e ad 663 5 has six p i ns as s o ciated with the jtag interface . t h e s e pi ns a r e use d to access t h e on-c hip te st access port and are listed i n t h e tab l e b e l o w. all inpu t jta g pi ns are pul l up exce pt fo r tc l k , w h i c h i s a p u l l do w n . name descripti o n /trst test access port reset t c l k t e s t c l o c k tms0 test access port mode select 0 tms1 test access port mode select 1 td i t e s t d a ta i n p u t t d o t e s t data out p u t ta bl e 1 9 . b o u n dar y sca n test pi ns rev. pr b. 7 / 25/2002 59
preliminary technical data AD6635 60 rev. pr b. 7 / 25/2002 tms0 is used to access channels 0 to 3, input / output ports a and b and halfband / agcs a and b. tms1 is used to access channels 4 to 7, input / output ports c and d and halfband / agcs c and d. the AD6635 supports four op codes as shown below. these instructions set the m ode of the jtag interface. instruction op code idcode 001 bypass 111 sample/preload 010 extest 000 highz 011 clamp 100 table 20. boundary scan op codes the vendor identification co de can be accessed through the idcode instruction and has the following format. msb version part number manufacturing id # lsb mandatory 0000 0010 0111 1000 1100 000 1110 0101 1 table 21. vendor id code a bsdl file for this device is available, please contact analog devices inc. for more information. extest (3'b000) -> places the ic into an external boundary-test mode and selects the boundary-scan register to be connected between tdi and tdo. during this, the boundary-scan register is acce ssed to drive test data off- chip via boundary outputs an d receive test data off-chip from boundary inputs. idcode (3'b001) -> allows the ic to remain in its functional mode and selects device id register to be connected between tdi and tdo. accessing the id register does not interfere wi th the operation of the ic. sample/preload (3'b010) -> allows the ic to remain in normal functional mode and selects the boundary-scan register to be connected between tdi and tdo. the boundary-scan regist er can be accessed by a scan operation to take a sample of the functional data entering and leaving the ic. also, test data can be preloaded into the boundary scan register before an extest instruction. highz (3'b011) -> sets all outputs to high impedance state. selects one-bit bypass register to be connected between tdi and tdo. clamp (3'b100) -> sets the outputs of the ic to logic levels determined by the boundary-scan register and selects one-bit bypass register to be connected between tdi and tdo. before this instruction, boundary-scan data can be preloaded with the sample/preload instruction. bypass (3'b111) -> allows the ic to remain in normal functional mode and selects one-bit bypass register between tdi and tdo. during this instruction, serial data is transferred from tdi to tdo without affecting operation of the ic. internal write access up to 20-bits of data (as needed) can be written by the process described below. any high order bytes that are needed are written to the corresponding data registers defined in the external 3-b it address space. the least significant byte is then written to dr0 at address (000). when a write to dr0 is detected, the internal microprocessor port state mach ine then moves the data in dr2-dr0 to the internal address pointed to by the address in the lar and amr. write pseudocode void write_micro(ext_address, int data); main(); { /* this code shows the programming of the nco phase offset register using the write_micro function as defined above. the variable address is the external address a[2:0] and data is the value to be placed in the external interface register. internal address = 0x087 */ // holding registers for nco phase byte wide access data int d1, d0; // nco phase word (16-bits wide) nco_phase = 0xcbef; // write acr write_micro(7, 0x03 ); // write car write_micro(6, 0x87); // write dr1 with d[15:8] d1 = (nco_phase & 0xff00) >> 8; write_micro(1, d1); // write dr0 with d[7:0] // on this write all data is transferred to the internal address d0 = nco_phase & 0xff; write_micro(0, d0); } // end of main
preliminary technical data AD6635 rev. pr b. 7 / 25/2002 61 internal read access a read is performed by first writing the car and amr as with a write. the data registers (dr2-dr0) are then read in the reverse order that they were written. first, the least significant byte of the data (d[7:0]) is read from dr0. on this transaction the high bytes of the data are moved from the internal address pointed to by the car and amr into the remaining data registers (dr2-dr1). this data can then be read from the data registers using the appropriate 3 bit addresses. the number of data registers used depends solely on the amount of data to be read or written. any unused bit in a data register should be masked out for a read. read pseudocode int read_micro(ext_address); main(); { /* this code shows the reading of the first rcf coefficient using the read_micro function as defined above. the variable address is the external address a[2..0]. internal address = 0x000 */ // holding registers for the coefficient int d2, d1, d0; // coefficient (20-bits wide) long coefficient; // write amr write_micro(7, 0x00 ); // write lar write_micro(6, 0x00); /* read d[7:0] from dr0, all data is moved from the internal registers to the inte rface registers on this access */ d0 = read_micro(0) & 0xff; // read d[15:8] from dr1 d1 = read_micro(1) & 0xff; // read d[23:16] from dr2 d2 = read_micro(2) & 0x0f; coefficient = d0 + (d 1 << 8) + (d2 << 16); } // end of main
preliminary technical data AD6635 62 rev. pr b. 7 / 25/2002 notes
preliminary technical data AD6635 rev. pr b. 7 / 25/2002 63 notes
preliminary technical data AD6635 64 rev. pr b. 7/25/2002 notes

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